Elevated source drain semiconductor device with L-shaped spacers and fabricating method thereof
First Claim
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1. A semiconductor device, comprising:
- a gate on a substrate;
a gate insulating layer along a sidewall and a bottom surface of the gate;
elevated source/drain regions formed on either side of the gate; and
an L-shaped spacer structure between the gate and the elevated source/drain regions, wherein the spacer structure exposes a top surface of the elevated source/drain regions,wherein the spacer structure includes a first portion along the sidewall of the gate and a second portion connected to the first portion and along a top surface of the substrate, extending beyond the portion along the sidewall of the gate, thereby extending the distance between the gate and source/drain regions on either side of the gate by a distance greater than the thickness of the spacer structure,wherein the spacer structure includes first through nth spacers that are sequentially stacked, and n denotes a natural number greater than or equal to “
2”
,wherein the nth spacer disposed at an outermost portion in the spacer structure is provided in an L shape,wherein a low doped drain (LDD) region is disposed in a lower portion of the spacer structure,wherein a bottom surface of the spacer structure contacts with the low doped drain region and does not contact with the elevated source/drain regions.
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Abstract
A semiconductor device includes a gate on a substrate, a gate insulating layer along a sidewall and a bottom surface of the gate, and an L-shaped spacer structure on both sidewalls of the gate. A structure extends the distance between the gate and source/drain regions to either side of the gate.
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Citations
20 Claims
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1. A semiconductor device, comprising:
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a gate on a substrate; a gate insulating layer along a sidewall and a bottom surface of the gate; elevated source/drain regions formed on either side of the gate; and an L-shaped spacer structure between the gate and the elevated source/drain regions, wherein the spacer structure exposes a top surface of the elevated source/drain regions, wherein the spacer structure includes a first portion along the sidewall of the gate and a second portion connected to the first portion and along a top surface of the substrate, extending beyond the portion along the sidewall of the gate, thereby extending the distance between the gate and source/drain regions on either side of the gate by a distance greater than the thickness of the spacer structure, wherein the spacer structure includes first through nth spacers that are sequentially stacked, and n denotes a natural number greater than or equal to “
2”
,wherein the nth spacer disposed at an outermost portion in the spacer structure is provided in an L shape, wherein a low doped drain (LDD) region is disposed in a lower portion of the spacer structure, wherein a bottom surface of the spacer structure contacts with the low doped drain region and does not contact with the elevated source/drain regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A semiconductor device, comprising:
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a gate on a substrate; a gate insulating layer along a sidewall and bottom surface of the gate; elevated source/drain regions formed on either side of the gate; an L-shaped spacer structure between the gate and the elevated source/drain regions, wherein the spacer structure exposes a top surface of the elevated source/drain regions; and a low doped drain (LDD) region between the spacer structure and elevated source/drain regions, wherein the spacer structure includes a first portion along the sidewall of the gate and as second portion connected to the first portion and along a top surface of the substrate, wherein the spacer structure includes first through nth spacers that are sequentially stacked, and n denotes a natural number greater than or equal to “
2”
,wherein the nth spacer disposed at an outermost portion in the spacer structure is provided in an L shape. - View Dependent Claims (15, 16)
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17. A semiconductor device, comprising:
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a gate on a substrate; a gate insulating layer along a sidewall and bottom surface of the gate; elevated source/drain regions formed on either side of the gate; an L-shaped spacer structure between the gate and the elevated source/drain regions, wherein the spacer structure exposes a top surface of the elevated source/drain regions; a low doped drain (LDD) region between the spacer structure and elevated source/drain regions; and a passivation layer conformally formed along the side surface of the L-shaped spacer structures and the top surface of the elevated source/drain regions, wherein the spacer structure includes a first portion along the sidewall of the gate and a second portion connected to the first portion and along a top surface of the substrate, wherein the spacer structure includes first through nth spacers that are sequentially stacked, and n denotes a natural number greater than or equal to “
2”
,wherein the nth spacer disposed at an outermost portion in the spacer structure is provided in an L shape. - View Dependent Claims (18, 19, 20)
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Specification