Elevated source drain semiconductor device with L-shaped spacers and fabricating method thereof

• US 9,831,240 B2
• Filed: 01/29/2014
• Issued: 11/28/2017
• Est. Priority Date: 07/12/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: Park, Min-Yeop, Daniele, Leonelli, Maeda, Shigenobu, Oh, Han-Su, Kim, Woong-Gi, Lee, Jong-Hyuk, Jeong, Ju-Seob
• Primary Examiner(s): Cao, Phat X
• Assistant Examiner(s): Hoque, Mohammad M
• Application Number:
  US14/167,236
• Publication Number:
  US 20150014788A1
• Time in Patent Office: 1,399 Days
• Field of Search: 257401
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device includes a gate on a substrate, a gate insulating layer along a sidewall and a bottom surface of the gate, and an L-shaped spacer structure on both sidewalls of the gate. A structure extends the distance between the gate and source/drain regions to either side of the gate.

Claims

1. A semiconductor device, comprising:

a gate on a substrate;

a gate insulating layer along a sidewall and a bottom surface of the gate;

elevated source/drain regions formed on either side of the gate; and

an L-shaped spacer structure between the gate and the elevated source/drain regions, wherein the spacer structure exposes a top surface of the elevated source/drain regions,

wherein the spacer structure includes a first portion along the sidewall of the gate and a second portion connected to the first portion and along a top surface of the substrate, extending beyond the portion along the sidewall of the gate, thereby extending the distance between the gate and source/drain regions on either side of the gate by a distance greater than the thickness of the spacer structure,

wherein the spacer structure includes first through n^th spacers that are sequentially stacked, and n denotes a natural number greater than or equal to “

2”

,

wherein the n^th spacer disposed at an outermost portion in the spacer structure is provided in an L shape,

wherein a low doped drain (LDD) region is disposed in a lower portion of the spacer structure,

wherein a bottom surface of the spacer structure contacts with the low doped drain region and does not contact with the elevated source/drain regions.

2. The semiconductor device of claim 1, wherein the top surface of the gate and a top surface of the first portion are disposed on the same plane.

3. The semiconductor device of claim 1, wherein a width of the first portion is constant.

4. The semiconductor device of claim 1, wherein each of the first through n^th spacers is provided in an L shape.

5. The semiconductor device of claim 1, wherein the spacer structure directly contacts with an interlayer insulating layer, and the interlayer insulating layer directly contacts with a sidewall of the first portion and a top surface of the second portion of the spacer structure.

6. The semiconductor device of claim 5, wherein the interlayer insulating layer includes a passivation layer formed along a side surface of the spacer structure and a top surface of elevated source/drain.

7. The semiconductor device of claim 1, further comprising:

elevated source/drain within a fin on both sides of the gate and contacting with the spacer structure.

8. The semiconductor device of claim 7, further comprising:

a first plug dopant region extended to an inside of the elevated source and a lower portion of the spacer structure and a second plug dopant region formed within the elevated drain.

9. The semiconductor device of claim 8, wherein the second plug dopant region is not overlapped with the spacer structure.

10. The semiconductor device of claim 1, further comprising:

an inner spacer between the spacer structure and the gate.

11. The semiconductor device of claim 10, wherein the inner spacer is provided in a chamfered I shape.

12. The semiconductor device of claim 1, wherein the elevated source/drain is an epitaxial layer.

13. The semiconductor device of claim 1, wherein the low doped drain (LDD) region is a portion of the substrate.

14. A semiconductor device, comprising:

a gate on a substrate;

a gate insulating layer along a sidewall and bottom surface of the gate;

elevated source/drain regions formed on either side of the gate;

an L-shaped spacer structure between the gate and the elevated source/drain regions, wherein the spacer structure exposes a top surface of the elevated source/drain regions; and

a low doped drain (LDD) region between the spacer structure and elevated source/drain regions, wherein the spacer structure includes a first portion along the sidewall of the gate and as second portion connected to the first portion and along a top surface of the substrate,

wherein the spacer structure includes first through n^th spacers that are sequentially stacked, and n denotes a natural number greater than or equal to “

2”

,

wherein the n^th spacer disposed at an outermost portion in the spacer structure is provided in an L shape.

15. The semiconductor device of claim 14, wherein the elevated source/drain is an epitaxial layer.

16. The semiconductor device of claim 14, wherein the low doped drain (LDD) region is a portion of the substrate.

17. A semiconductor device, comprising:

a gate on a substrate;

a gate insulating layer along a sidewall and bottom surface of the gate;

elevated source/drain regions formed on either side of the gate;

an L-shaped spacer structure between the gate and the elevated source/drain regions, wherein the spacer structure exposes a top surface of the elevated source/drain regions;

a low doped drain (LDD) region between the spacer structure and elevated source/drain regions; and

a passivation layer conformally formed along the side surface of the L-shaped spacer structures and the top surface of the elevated source/drain regions,

wherein the spacer structure includes a first portion along the sidewall of the gate and a second portion connected to the first portion and along a top surface of the substrate,

wherein the spacer structure includes first through n^th spacers that are sequentially stacked, and n denotes a natural number greater than or equal to “

2”

,

wherein the n^th spacer disposed at an outermost portion in the spacer structure is provided in an L shape.

18. The semiconductor device of claim 17, wherein the low doped drain (LDD) region is disposed in a lower portion of the spacer structure, wherein a bottom surface of the spacer structure contacts with the low doped drain region and does not contact with the elevated source/drain region.

19. The semiconductor device of claim 17, wherein the elevated source/drain is an epitaxial layer.

20. The semiconductor device of claim 17, wherein the low doped drain (LDD) region is a portion of the substrate.