Electronic device package and fabricating method thereof

• US 9,831,282 B2
• Filed: 08/26/2016
• Issued: 11/28/2017
• Est. Priority Date: 11/20/2012
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Kim, Jin Young, Park, No Sun, Kim, Yoon Joo, Lee, Seung Jae, Cha, Se Woong, Kim, Sung Kyu, Yoon, Ju Hoon
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US15/248,687
• Publication Number:
  US 20160365379A1
• Time in Patent Office: 459 Days
• CPC Class Codes: G06V 40/12 Fingerprints or palmprints
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/211 Disposition
• CPC Class Codes: H01L 2224/214 Connecting portions
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14678 Contact-type imagers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/18162 of a chip with build-up interconnect

Abstract

Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 μm or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof.

Claims

1. A semiconductor device comprising:

a semiconductor die comprising a first die surface, a second die surface opposite the first die surface, and side die surfaces connecting the first and second die surfaces, where the first die surface comprises a bond pad;

an encapsulant covering at least one of the side die surfaces and comprising a first encapsulant surface and a second encapsulant surface opposite the first encapsulant surface;

a conductive via passing through at least the encapsulant between the first encapsulant surface and the second encapsulant surface, wherein the conductive via comprises a beveled side surface, and a first end of the conductive via is narrower than a second end of the conductive via;

a first conductive layer extending over at least a portion of the first die surface and over at least a portion of the first encapsulant surface, and electrically connected to the bond pad and the first end of the conductive via;

a second conductive layer extending over at least a portion of the second encapsulant surface, and electrically connected to the second end of the conductive via; and

an electrical interconnection structure coupled to the second conductive layer.

2. The semiconductor device of claim 1, wherein the second conductive layer does not directly contact the second encapsulant surface.

3. A semiconductor device comprising:

a semiconductor die comprising a first die surface, a second die surface opposite the first die surface, and side die surfaces connecting the first and second die surfaces, where the first die surface comprises a bond pad;

an encapsulant covering at least one of the side die surfaces and the second die surface, and comprising a first encapsulant surface and a second encapsulant surface opposite the first encapsulant surface;

a conductive via passing through at least the encapsulant between the first encapsulant surface and the second encapsulant surface;

a first conductive layer extending over at least a portion of the first die surface and over at least a portion of the first encapsulant surface, and electrically connected to the bond pad and a first end of the conductive via;

a second conductive layer extending over at least a portion of the second encapsulant surface, and electrically connected to a second end of the conductive via; and

an electrical interconnection structure coupled to the second conductive layer.

4. The semiconductor device of claim 3, wherein the second end of the conductive via is coplanar with the second encapsulant surface.

5. The semiconductor device of claim 3, wherein the encapsulant is the only insulation layer directly between the electrical interconnection structure and the semiconductor die.

6. A semiconductor device comprising:

a semiconductor die comprising a first die surface, a second die surface opposite the first die surface, and side die surfaces connecting the first and second die surfaces, where the first die surface comprises a bond pad;

an encapsulant covering at least one of the side die surfaces and comprising a first encapsulant surface and a second encapsulant surface opposite the first encapsulant surface;

a conductive via passing through at least the encapsulant between the first encapsulant surface and the second encapsulant surface;

a first conductive layer extending over at least a portion of the first die surface and over at least a portion of the first encapsulant surface, and electrically connected to the bond pad and a first end of the conductive via;

a second conductive layer extending over at least a portion of the second encapsulant surface, and electrically connected to a second end of the conductive via; and

an electrical interconnection structure coupled to the second conductive layer,

wherein a fan-in portion of the second conductive layer extends over at least a portion of the second die surface.

7. The semiconductor device of claim 6, wherein the electrical interconnection structure is attached to the fan-in portion of the second conductive layer.

8. A semiconductor device comprising:

a semiconductor die comprising a first die surface, a second die surface opposite the first die surface, and side die surfaces connecting the first and second die surfaces, where the first die surface comprises a bond pad;

an encapsulant covering at least one of the side die surfaces and comprising a first encapsulant surface and a second encapsulant surface opposite the first encapsulant surface;

a conductive via passing through at least the encapsulant between the first encapsulant surface and the second encapsulant surface;

a first conductive layer extending over at least a portion of the first die surface and over at least a portion of the first encapsulant surface, and electrically connected to the bond pad and a first end of the conductive via;

a second conductive layer extending over at least a portion of the second encapsulant surface, and electrically connected to a second end of the conductive via; and

an electrical interconnection structure coupled to the second conductive layer,

wherein the first conductive layer extends from the bond pad toward one of the side die surfaces and past the first end of the conductive via.

9. The semiconductor device of claim 8, comprising a dielectric layer that completely covers the first conductive layer.

10. A semiconductor device comprising:

a semiconductor die comprising a first die surface, a second die surface opposite the first die surface, and side die surfaces connecting the first and second die surfaces, where the first die surface comprises a bond pad, and wherein the semiconductor die is rectangular shaped with a first and second of the side die surfaces longer than a third and fourth of the side die surfaces;

an encapsulant covering at least one of the side die surfaces and comprising a first encapsulant surface and a second encapsulant surface opposite the first encapsulant surface;

a conductive via passing through at least the encapsulant between the first encapsulant surface and the second encapsulant surface;

a first conductive layer extending over at least a portion of the first die surface and over at least a portion of the first encapsulant surface, and electrically connected to the bond pad and a first end of the conductive via;

a second conductive layer extending over at least a portion of the second encapsulant surface, and electrically connected to a second end of the conductive via;

an electrical interconnection structure coupled to the second conductive layer; and

a first conductive trace, wherein;

the first conductive trace runs in a plane that is parallel to the first die surface and separated from the first die surface; and

the first conductive trace runs alongside the first side die surface along at least most of the length of the first side die surface.

11. The semiconductor device of claim 10, comprising a second conductive trace, wherein:

the second conductive trace runs in the plane that is parallel to the first die surface and separated from the first die surface; and

the second conductive trace runs alongside the second side die surface along at least most of the length of the second side die surface.

12. The semiconductor device of claim 10, wherein the encapsulant covers the second die surface.

13. The semiconductor device of claim 12, wherein the second end of the conductive via is coplanar with the second encapsulant surface.

14. The semiconductor device of claim 12, wherein the encapsulant is the only insulation layer directly between the electrical interconnection structure and the semiconductor die.

15. The semiconductor device of claim 10, wherein the first conductive layer extends from the bond pad toward one of the side die surfaces and past the first end of the conductive via.

16. A semiconductor device comprising:

a semiconductor die comprising a first die surface, a second die surface opposite the first die surface, and side die surfaces connecting the first and second die surfaces, where the first die surface comprises a bond pad;

an encapsulant covering at least one of the side die surfaces and comprising a first encapsulant surface and a second encapsulant surface opposite the first encapsulant surface;

a conductive via passing through at least the encapsulant between the first encapsulant surface and the second encapsulant surface;

a first conductive layer extending over at least a portion of the first die surface and over at least a portion of the first encapsulant surface, and electrically connected to the bond pad and a first end of the conductive via;

a dielectric layer that completely covers at least a side of the first conductive layer facing away from the semiconductor die;

a second conductive layer extending over at least a portion of the second encapsulant surface, and electrically connected to a second end of the conductive via; and

an electrical interconnection structure coupled to the second conductive layer.

17. The semiconductor device of claim 16, wherein there are no apertures extending completely through the dielectric layer.

18. The semiconductor device of claim 16, wherein the encapsulant covers the second die surface.

19. The semiconductor device of claim 18, wherein the second end of the conductive via is coplanar with the second encapsulant surface.

20. The semiconductor device of claim 18, wherein the encapsulant is the only insulation layer directly between the electrical interconnection structure and the semiconductor die.