Making electrical components in handle wafers of integrated circuit packages

• US 9,831,302 B2
• Filed: 11/23/2016
• Issued: 11/28/2017
• Est. Priority Date: 05/02/2014
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Wang, Liang, Shen, Hong, Katkar, Rajesh
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US15/360,121
• Publication Number:
  US 20170077076A1
• Time in Patent Office: 370 Days
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/11 the devices being of a type provided for in group H01L29/00
• CPC Class Codes: H01L 25/115 the devices being arranged next to each other
• CPC Class Codes: H01L 25/165 Containers
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 : Electrodes
• CPC Class Codes: H01L 28/65 : comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1205 : Capacitor
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16153 : Cap enclosing a plurality of side-by-side cavities [e.g. E-shaped cap]

Abstract

A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

Claims

1. An integrated circuit package comprising a first substrate and a second substrate bonded to the first substrate, with a plurality of cavities enclosed by the first and second substrates, the plurality of cavities comprising one or more first cavities and one or more second cavities;

wherein the second substrate comprises circuitry with first electroconductive pads in the first and second cavities, each of the first and second cavities having at least one first electroconductive pad therein; and

wherein the integrated circuit package further comprises;

in each first cavity, at least one semiconductor die comprising an integrated circuit electroconductively coupled to at least one first electroconductive pad in the first cavity; and

in each second cavity, at least one discrete electrical component electroconductively coupled to at least one first electroconductive pad in the second cavity and comprising a conductive layer such that at least one of the following is true;

(i) the conductive layer is formed over a surface of the first substrate in the second cavity;

(ii) the conductive layer comprises at least a part of the surface of the first substrate in the second cavity.

2. The integrated circuit package of claim 1 wherein the first substrate is a semiconductor substrate, and in at least one second cavity the conductive layer is a doped layer comprising at least said part of the surface of the first substrate.

3. The integrated circuit package of claim 1 wherein in at least one second cavity the conductive layer is formed over the surface of the first substrate.

4. The integrated circuit package of claim 1 wherein in at least one second cavity, at least one discrete electrical component is a capacitor, and the conductive layer is a first plate of the capacitor.

5. The integrated circuit package of claim 4 wherein in said at least one second cavity, the surface of the first substrate in the cavity comprises one or more rods or ridges increasing a capacitance of the capacitor.

6. The integrated circuit package of claim 5 wherein in said at least one second cavity:

the capacitor comprises a second plate and a dielectric layer between the first and second plates; and

the surface of the first substrate in the cavity comprises one or more rods or ridges increasing an area of each of the first and second plates.

7. The integrated circuit package of claim 4 wherein in at least one second cavity:

the capacitor comprises a second plate and a dielectric layer between the first and second plates; and

the surface of the first substrate in the cavity comprises one or more rods or ridges increasing an area of each of the first and second plates.

8. The integrated circuit package of claim 1 wherein the circuitry of the second substrate further comprises a second electroconductive pad not covered by the first substrate and comprises a conductive line connecting the second electroconductive pad to at least one first electroconductive pad in a second cavity.

9. The integrated circuit package of claim 1 wherein the circuitry of the second substrate comprises an electroconductive via connected to at least one first electroconductive pad and passing through the second substrate.

10. The integrated circuit package of claim 1 wherein at least one second cavity does not contain any integrated circuit.

11. A fabrication method comprising:

obtaining a first substrate;

forming one or more features each of which comprises a conductive layer such that at least one of the following is true;

(i) the conductive layer is formed over a surface of the first substrate;

(ii) the conductive layer comprises a part of the surface of the first substrate;

providing a second substrate comprising circuitry comprising one or more first electroconductive pads;

obtaining one or more semiconductor dies each of which comprises an integrated circuit;

attaching together the first substrate, the second substrate, and the one or more semiconductor dies to obtain a structure with a plurality of cavities enclosed by the first and second substrates, the plurality of cavities comprising one or more first cavities and one or more second cavities, each of the first and second cavities having at least one first electroconductive pad therein, such that each first cavity contains at least one said semiconductor die comprising the integrated circuit electroconductively coupled to at least one first electroconductive pad in the first cavity, and each second cavity contains at least one discrete electrical component comprising at least one said feature and electroconductively coupled to at least one first electroconductive pad in the first cavity.

12. A fabrication method comprising:

obtaining a first substrate;

forming one or more features each of which comprises a conductive layer such that at least one of the following is true;

(i) the conductive layer is formed over a surface of the first substrate;

(ii) the conductive layer comprises a part of the surface of the first substrate;

providing a second substrate comprising circuitry comprising one or more first electroconductive pads;

obtaining one or more semiconductor dies each of which comprises an integrated circuit;

attaching together the first substrate, the second substrate, and the one or more semiconductor dies to obtain a structure with a plurality of cavities enclosed by the first and second substrates, the plurality of cavities comprising one or more first cavities and one or more second cavities, each of the first and second cavities having at least one first electroconductive pad therein, such that each first cavity contains at least one said semiconductor die comprising the integrated circuit electroconductively coupled to at least one first electroconductive pad in the first cavity, and each second cavity contains at least one discrete electrical component comprising at least one said feature and electroconductively coupled to at least one first electroconductive pad in the second cavity;

wherein in at least one second cavity, at least one discrete electrical component is a capacitor, and the conductive layer is a first plate of the capacitor.

13. The method of claim 12 wherein the first substrate is a semiconductor substrate, and in at least one said discrete electrical component at least one said feature comprises a doped part of the surface of the first substrate.

14. The method of claim 13 wherein in at least one said feature of at least one said discrete electrical component, the conductive layer is formed over the surface of the first substrate.

15. The method of claim 12 wherein in said at least one second cavity, the surface of the first substrate in the cavity comprises one or more rods or ridges increasing a capacitance of the capacitor.

16. The method of claim 12 wherein in said at least one second cavity, the capacitor comprises a second plate and a dielectric layer between the first and second plates;

and

the surface of the first substrate in the cavity comprises one or more rods or ridges increasing an area of each of the first and second plates.

17. The method of claim 12 wherein in said at least one second cavity, the capacitor comprises a second plate and a dielectric layer between the first and second plates;

and

the surface of the first substrate in the cavity comprises one or more rods or ridges increasing an area of each of the first and second plates.

18. A fabrication method comprising:

obtaining a first substrate;

forming one or more features each of which comprises a conductive layer such that at least one of the following is true;

(i) the conductive layer is formed over a surface of the first substrate;

(ii) the conductive layer comprises a part of the surface of the first substrate;

providing a second substrate comprising circuitry comprising one or more first electroconductive pads;

obtaining one or more semiconductor dies each of which comprises an integrated circuit;

attaching together the first substrate, the second substrate, and the one or more semiconductor dies to obtain a structure with a plurality of cavities enclosed by the first and second substrates, the plurality of cavities comprising one or more first cavities and one or more second cavities, each of the first and second cavities having at least one first electroconductive pad therein, such that each first cavity contains at least one said semiconductor die comprising the integrated circuit electroconductively coupled to at least one first electroconductive pad in the first cavity, and each second cavity contains at least one discrete electrical component comprising at least one said feature and electroconductively coupled to at least one first electroconductive pad in the second cavity;

wherein the circuitry of the second substrate further comprises a second electroconductive pad not covered by the first substrate and comprises a conductive line connecting the first electroconductive pad to at least one first electroconductive pad in a second cavity.

19. The method of claim 18 wherein the circuitry of the second substrate comprises an electroconductive via connected to at least one first electroconductive pad and passing through the second substrate.

20. The method of claim 18 wherein after said attaching, at least one second cavity does not contain any integrated circuit.