Semiconductor device and method of manufacturing semiconductor device

• US 9,831,316 B2
• Filed: 07/10/2015
• Issued: 11/28/2017
• Est. Priority Date: 07/11/2014
• Status: Active Grant

• Current Assignee: Shindengen Electric Manufacturing Company Limited
• Original Assignee: Shindengen Electric Manufacturing Company Limited
• Inventors: Inoue, Tetsuto, Sugai, Akihiko, Nakamura, Shunichi
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Kim, Tong-Ho
• Application Number:
  US15/303,730
• Publication Number:
  US 20170040423A1
• Time in Patent Office: 872 Days
• Field of Search: 257 77, 257330
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/12 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/739 controlled by field-effect, e.g. bipolar static induction transistors [BSIT] unijunction transistors H01L29/705
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes an element portion and a gate pad portion on the same wide gap semiconductor substrate. The element portion includes a first trench structure having a plurality of first protective trenches and first buried layers formed deeper than gate trenches. The gate pad portion includes a second trench structure having a plurality of second protective trenches and second buried layers. The second trench structure is either one of a structure where the second trench structure includes: a p-type second semiconductor region and a second buried layer made of a conductor or a structure where the second trench structure includes a second buried layer formed of a metal layer which forms a Schottky contact. The second buried layer is electrically connected with the source electrode layer.

Claims

1. A semiconductor device comprising:

a wide gap semiconductor substrate;

an element portion formed on the wide gap semiconductor substrate, the element portion comprising;

a low resistance semiconductor layer of a first conductive type;

a drift layer of a first conductive type having a lower density of impurity than the low resistance semiconductor layer;

a body layer of a second conductive type opposite to the first conductive type, the body layer positioned over the drift layer;

a gate trench formed so as to open in the body layer and to reach the drift layer;

a source region of the first conductive type formed in a state where the source region is arranged in the inside of the body layer and at least a portion of the source region is exposed on an inner peripheral surface of the gate trench;

a gate insulation layer formed on the inner peripheral surface of the gate trench;

a gate electrode layer formed inside the gate trench by way of the gate insulation layer; and

a source electrode layer formed in a state where the source electrode layer is insulated from the gate electrode layer and is brought into contact with the source region; and

a gate pad portion formed on the wide gap semiconductor substrate, the gate pad portion comprising;

a low resistance semiconductor layer of a first conductive type;

a drift layer of the first conductive type having a lower density of impurity than the low resistance semiconductor layer;

a second-conductive-type semiconductor layer of the second conductive type positioned on the drift layer;

an insulation layer formed on the second-conductive-type semiconductor layer; and

a gate line formed on the insulation layer, wherein

the element portion further includes a first trench structure which has;

a plurality of first protective trenches where the first protective trenches open in the body layer in a region between the gate trenches formed adjacently to each other and are formed deeper than the gate trenches and shallower than the low resistance semiconductor layer; and

a first buried layer formed inside the respective first protective trenches, and

the gate pad portion further includes a second trench structure which has;

a plurality of second protective trenches where the second protective trenches open in the second-conductive-type semiconductor layer and are formed deeper than the gate trenches and shallower than the low resistance semiconductor layer; and

a second buried layer formed inside the respective second protective trenches,

the first trench structure is either one of a structure where the first trench structure further includes a first semiconductor region of the second conductive type formed on at least a bottom portion of the first protective trench and a first buried layer which is made of a conductor as the first buried layer, and the first buried layer is connected with the drift layer through the first semiconductor region or a structure where the first trench structure includes a first buried layer which is formed of a metal layer forming a Schottky contact with the drift layer on a bottom portion and a side portion of the first protective trench as the first buried layer and the first buried layer forms the drift layer and the Schottky contact,

the second trench structure is either one of a structure where the second trench structure further includes a second semiconductor region of the second conductive type formed on at least a bottom portion of the second protective trench and a second buried layer which is made of a conductor as the second buried layer, and the second buried layer is connected with the drift layer through the second semiconductor region or a structure where the second trench structure includes a second buried layer which is formed of a metal layer forming a Schottky contact with the drift layer on a bottom portion and a side portion of the second protective trench as the second buried layer and the second buried layer forms the drift layer and the Schottky contact, and

the first buried layer and the second buried layer are electrically connected with the source electrode layer.

2. The semiconductor device according to claim 1, wherein a depth of the second protective trench is equal to a depth of the first protective trench.

3. The semiconductor device according to claim 1, wherein a width of an opening formed in the second protective trench is equal to a width of an opening formed in the first protective trench.

4. The semiconductor device according to claim 1, wherein the second protective trench extends to a region where the element portion is formed as viewed in a plan view.

5. The semiconductor device according to claim 4, wherein the second protective trench is formed in a state where the second protective trench is continuously formed with the first protective trench.

6. The semiconductor device according to claim 1, wherein the second trench structure further includes a second semiconductor region of a second conductive type formed on at least a bottom portion of the second protective trench, and includes a second buried layer made of a conductor as the second buried layer, and

the second trench structure further includes:

a second side wall insulation layer formed on a side portion of the second protective trench; and

a second semiconductor region formed on a bottom portion of the second protective trench as the second semiconductor region.

7. The semiconductor device according to claim 1, wherein the second trench structure further includes a second semiconductor region of a second conductive type formed on at least a bottom portion of the second protective trench, and includes a second buried layer made of a conductor as the second buried layer, and

the second trench structure further includes:

a second side wall insulation layer formed on a side portion of the second protective trench; and

a second semiconductor region formed in a position surrounding the second buried layer and the second side wall insulation layer on a bottom portion and a side portion of the second protective trench as the second semiconductor region.

8. The semiconductor device according to claim 1, wherein the second trench structure further includes a second semiconductor region of a second conductive type formed on at least a bottom portion of the second protective trench, and includes a second buried layer made of a conductor as the second buried layer, and

the second trench structure includes a second semiconductor region formed on a bottom portion and a side portion of the second protective trench as the second semiconductor region.

9. The semiconductor device according to claim 1, wherein the element portion further has a third trench structure which has the same structure as the first trench structure on a more gate pad portion side than a gate trench closest to the gate pad portion among the plurality of gate trenches.

10. A method of manufacturing a semiconductor device for manufacturing the semiconductor device according to claim 1, the method comprising:

a wide gap semiconductor substrate preparing step of preparing the wide gap semiconductor substrate on which the element portion which includes;

the low resistance semiconductor layer of a first conductive type;

the drift layer of the first conductive type having a lower density of impurity than the low resistance semiconductor layer;

the body layer of the second conductive type opposite to the first conductive type, the body layer positioned over the drift layer; and

the source region of the first conductive type formed in the inside of the body layer; and

the gate pad portion which includes;

the low resistance semiconductor layer of a first conductive type;

the drift layer of the first conductive type having a lower density of impurity than the low resistance semiconductor layer; and

the second-conductive-type semiconductor layer of the second conductive type positioned on the drift layer;

a protective trench forming step of forming collectively, the plurality of first protective trenches where the first protective trenches open in predetermined regions of the body layer to be shallower than the low resistance semiconductor layer in the element portion and the plurality of second protective trenches where the second protective trenches open in predetermined regions of the second-conductive-type semiconductor layer of the second conductive type to be shallower than the low resistance semiconductor layer in the gate pad portion;

a second semiconductor region forming step of forming the second semiconductor region of the second conductive type on at least the bottom portion of the second protective trench;

a gate trench structure forming step of forming the gate trench such that the gate trench opens in the body layer and reaches the drift layer, the gate insulation layer formed on the inner peripheral surface of the gate trench, and the gate electrode layer formed inside the gate trench by way of the gate insulation layer;

a buried layer forming step of forming a first buried layer inside the respective first protective trenches in the element portion, and forming a second buried layer made of a conductor inside the respective second protective trenches in the gate pad portion; and

an electrode layer and wiring forming step of forming a source electrode layer in a state where the source electrode layer is insulated from the gate electrode layer and is brought into contact with the source region in the element portion, and forming an insulation layer on the second-conductive-type semiconductor layer and forming a gate line on the insulation layer in the gate pad portion in this order, and

the second buried layer is electrically connected to the source electrode layer.

11. A method of manufacturing a semiconductor device for manufacturing the semiconductor device according to claim 1, the method comprising:

a wide gap semiconductor substrate preparing step of preparing the wide gap semiconductor substrate on which the element portion which includes;

the low resistance semiconductor layer of a first conductive type;

the drift layer of the first conductive type having a lower density of impurity than the low resistance semiconductor layer;

the body layer of the second conductive type opposite to the first conductive type, the body layer positioned over the drift layer; and

the source region of the first conductive type formed in the inside of the body layer; and

the gate pad portion which includes;

the low resistance semiconductor layer of a first conductive type;

the drift layer of the first conductive type having a lower density of impurity than the low resistance semiconductor layer; and

the second-conductive-type semiconductor layer of the second conductive type which is positioned on the drift layer;

a protective trench forming step of forming collectively, the plurality of first protective trenches where the first protective trenches open in predetermined regions of the body layer to be shallower than the low resistance semiconductor layer in the element portion and the plurality of second protective trenches where the second protective trenches open in predetermined regions of the second-conductive-type semiconductor layer to be shallower than the low resistance semiconductor layer in the gate pad portion;

a gate trench structure forming step of forming the gate trench such that the gate trench opens in the body layer and reaches the drift layer, the gate insulation layer formed on the inner peripheral surface of the gate trench, and the gate electrode layer formed inside the gate trench by way of the gate insulation layer;

a buried layer forming step of forming a first buried layer inside the respective first protective trenches in the element portion, and forming a second buried layer formed of a metal layer which forms a Schottky contact with the drift layer on a bottom portion and a side portion of the second protective trench in the gate pad portion; and

an electrode layer and wiring forming step of forming a source electrode layer in a state where the source electrode layer is insulated from the gate electrode layer and is brought into contact with the source region in the element portion, and forming an insulation layer on the second-conductive-type semiconductor layer and forming a gate line on the insulation layer in the gate pad portion in this order, and

the second buried layer is electrically connected to the source electrode layer.