Semiconductor device

• US 9,831,335 B2
• Filed: 02/20/2015
• Issued: 11/28/2017
• Est. Priority Date: 02/20/2015
• Status: Active Grant

• Current Assignee: Shindengen Electric Manufacturing Company Limited
• Original Assignee: Shindengen Electric Manufacturing Company Limited
• Inventors: Kishi, Masato, Watanabe, Yuji, Takemori, Toshiyuki, Anazawa, Takeo, Akimoto, Toshitaka
• Primary Examiner(s): Blum, David S
• Application Number:
  US15/514,615
• Publication Number:
  US 20170222037A1
• Time in Patent Office: 1,012 Days
• Field of Search: 257330
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/435 Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Provided is a semiconductor apparatus includes: a gate electrode disposed inside a trench and opposedly facing a p type base region with a gate insulating film interposed therebetween on a portion of a side wall; a shield electrode disposed inside the trench and positioned between the gate electrode and a bottom of the trench; an electric insulating region disposed inside the trench, the electric insulating region expanding between the gate electrode and the shield electrode, and further expanding along the side wall and the bottom of the trench so as to separate the shield electrode from the side wall and the bottom; a source electrode electrically connected to an n⁺ type source region and the shield electrode, wherein the shield electrode has a high resistance region positioned on an n⁺ drain region side, and a low resistance region positioned on a gate electrode side.

Claims

1. A semiconductor device comprising:

a semiconductor base body having a drain region of a first conductive type, a drift region of the first conductive type disposed adjacently to the drain region, a base region of a second conductive type disposed adjacently to the drift region, and a source region of the first conductive type disposed adjacently to the base region, and having a trench in the inside of there, the trench having a bottom disposed adjacently to the drift region and a side wall disposed adjacently to the base region and the drift region, the trench being formed into a stripe pattern as viewed in a plan view;

a gate electrode disposed in the inside of the trench and opposedly facing the base region with a gate insulating film interposed therebetween on a portion of the side wall;

a shield electrode disposed in the inside of the trench and positioned between the gate electrode and the bottom of the trench;

an electric insulating region disposed in the inside of the trench, the electric insulating region expanding between the gate electrode and the shield electrode, and further expanding along the side wall and the bottom of the trench so as to separate the shield electrode from the side wall and the bottom;

a source electrode formed above the semiconductor base body and electrically connected to the source region and the shield electrode; and

a drain electrode formed adjacently to the drain region, wherein

the shield electrode has a high resistance region positioned on a drain region side, and a low resistance region positioned on a gate electrode side.

2. The semiconductor device according to claim 1, wherein both the high resistance region and the low resistance region are made of a same semiconductor material containing a dopant, and dopant concentration in the low resistance region is higher than dopant concentration in the high resistance region.

3. The semiconductor device according to claim 1, wherein the high resistance region and the low resistance region are made of different materials respectively, and electric resistivity of the material for forming the low resistance region is lower than electric resistivity of the material for forming the high resistance region.

4. The semiconductor device according to claim 1, wherein both the high resistance region and the low resistance region are made of a same material, and a cross-sectional area of the low resistance region taken along a plane orthogonal to a stripe longitudinal direction of the shield electrode is larger than a cross-sectional area of the high resistance region taken along a plane orthogonal to the stripe longitudinal direction of the shield electrode.

5. The semiconductor device according to claim 1, wherein the high resistance region and the low resistance region are disposed at a position where the high resistance region and the low resistance region are brought into contact with each other.

6. The semiconductor device according to claim 1, wherein the high resistance region and the low resistance region are disposed at positions spaced apart from each other with the electric insulating region interposed therebetween.

7. The semiconductor device according to claim 6, wherein in the electric insulating region, the electric insulating region sandwiched between the high resistance region and the low resistance region has an opening portion partially, and

the high resistance region and the low resistance region are brought into contact with each other partially through the opening portion.

8. The semiconductor device according to claim 2, wherein a thickness of the low resistance region is thinner than a thickness of the high resistance region.

9. The semiconductor device according to claim 2, wherein a thickness of the high resistance region is thinner than a thickness of the low resistance region.