Method to induce strain in 3-D microfabricated structures

• US 9,831,342 B2
• Filed: 12/18/2015
• Issued: 11/28/2017
• Est. Priority Date: 07/29/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Loubet, Nicolas, Morin, Pierre
• Primary Examiner(s): Pham, Hoai V
• Application Number:
  US14/975,534
• Publication Number:
  US 20160172497A1
• Time in Patent Office: 711 Days
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

Claims

1. A device, comprising:

a semiconductor substrate having a first surface and a second surface on a raised portion of the semiconductor substrate, the raised portion extending away from the first surface;

a first semiconductor layer on the raised portion of the semiconductor substrate;

a strained second semiconductor layer on the first semiconductor layer; and

a finFET transistor on the substrate, the finFET transistor including;

a fin formed from the first semiconductor layer and the strained second semiconductor layer; and

a strained channel formed in the strained second semiconductor layer in the fin.

2. The device of claim 1 wherein the fin includes the raised portion of the semiconductor substrate.

3. The device of claim 1 wherein the strained channel is configured to be strained in response to relaxation of the first semiconductor layer.

4. The device of claim 1, further comprising a dielectric layer over top and side surfaces of the fin and a gate electrode on the dielectric layer.

5. The device of claim 1 wherein the first semiconductor layer includes silicon germanium.

19. The device of claim 1 wherein the first semiconductor layer is relaxed based on the raised portion of the semiconductor substrate.

6. A device, comprising:

a strained silicon substrate;

a relaxed silicon germanium layer on the strained silicon substrate;

a strained silicon layer on the relaxed silicon germanium layer;

a transistor formed on the strained silicon substrate, the transistor including;

a channel region formed in the strained silicon layer; and

a gate adjacent to sidewalls of the strained silicon substrate, the relaxed silicon germanium layer, and the strained silicon layer.

7. The device of claim 6 wherein the transistor includes a fin, the fin being a three-dimensional structure extending from the strained silicon substrate, the fin including the relaxed silicon germanium layer and the strained silicon layer.

8. The device of claim 7 wherein the fin includes a portion of the strained silicon substrate.

9. The device of claim 7, further comprising a dielectric layer over top and side surfaces of the fin and a gate electrode on the dielectric layer.

10. The device of claim 9 wherein source and drain regions are formed in the strained silicon layer.

11. The device of claim 9 wherein a portion of the strained silicon substrate is in a space between a first portion and a second portion of the gate electrode.

12. A device, comprising:

a substrate;

a finFET transistor on the substrate, the finFET transistor including a fin structure, the fin structure including;

a strained portion of the substrate having a first length and a first width;

a strain-inducing layer on the strained portion of the substrate, the strain-inducing layer having the same length and width as the strained portion of the substrate; and

a semiconductor layer on the strain-inducing layer, the semiconductor layer including a strained-channel.

13. The device of claim 12 wherein the strain-inducing layer includes silicon germanium.

14. The device of claim 12 wherein the strain-inducing layer includes silicon carbide.

15. The device of claim 12 wherein the finFET transistor includes source and drain regions in the semiconductor layer.

16. The device of claim 12 wherein the finFET transistor includes an insulating layer over a portion of the fin.

17. The device of claim 16 wherein the finFET transistor includes a gate electrode is positioned over the insulating layer.

18. The device of claim 17 wherein the finFET transistor includes source and drain regions in the semiconductor layer adjacent to the portion of the fin.

20. The device of claim 12 wherein the semiconductor layer has the same length and width as the strain-inducing layer.