Semiconductor device

• US 9,831,351 B2
• Filed: 02/10/2016
• Issued: 11/28/2017
• Est. Priority Date: 09/24/2012
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): RAHMAN, MOIN M
• Application Number:
  US15/040,092
• Publication Number:
  US 20160155854A1
• Time in Patent Office: 657 Days
• Field of Search: 257 20, 257194, 257135-136, 257213-413, 257900, 257902-903
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.

Claims

1. A semiconductor device comprising:

a multi-layer film including a first oxide layer, an oxide semiconductor layer over the first oxide layer, and a second oxide layer over the oxide semiconductor layer;

a gate insulating film in contact with the multi-layer film;

a gate electrode overlapping with the multi-layer film with the gate insulating film therebetween; and

a protective layer over the gate electrode, the protective layer comprising a first layer and a second layer over the first layer,

wherein each of the first oxide layer, the second oxide layer, and the oxide semiconductor layer contains indium,

wherein the oxide semiconductor layer is in contact with each of the first oxide layer and the second oxide layer,

wherein an energy at a bottom of a conduction band of the first oxide layer is larger than an energy at a bottom of a conduction band of the oxide semiconductor layer,

wherein an energy at a bottom of a conduction band of the second oxide layer is larger than the energy at the bottom of the conduction band of the oxide semiconductor layer,

wherein at least one of the first oxide layer, the oxide semiconductor layer, the second oxide layer includes a crystal,

wherein a c-axis of the crystal is substantially parallel to a normal vector of a surface of the second oxide layer,

wherein a concentration of silicon in the oxide semiconductor layer is less than 1×

10¹⁹ atoms/cm³ ,

wherein the first layer comprises silicon oxide and is configured to release oxygen by heat treatment, and

wherein the second layer comprises silicon nitride which is configured to block oxygen.

2. The semiconductor device according to claim 1,

wherein a gap between the energy at the bottom of the conduction band of the first oxide layer and the energy at the bottom of the conduction band of the oxide semiconductor layer is greater than or equal to 0.05 eV and less than or equal to 2 eV, and

wherein a gap between the energy at the bottom of the conduction band of the second oxide layer and the energy at the bottom of the conduction band of the oxide semiconductor layer is greater than or equal to 0.05 eV and less than or equal to 2 eV.

3. The semiconductor device according to claim 1, further comprising:

a source electrode and a drain electrode, wherein each of the source electrode and the drain electrode is in contact with side edges of the oxide semiconductor layer.

4. The semiconductor device according to claim 1,

wherein each of the oxide semiconductor layer, the first oxide layer, and the second oxide layer comprises at least one of indium, zinc, and a metal,

wherein the metal is selected from aluminum, titanium, gallium, yttrium, zirconium, tin, lanthanum, cerium, neodymium, and hafnium, and

wherein an atomic ratio of indium to the metal in each of the first oxide layer and the second oxide layer is lower than an atomic ratio of indium to the metal in the oxide semiconductor layer.

5. The semiconductor device according to claim 1, wherein a carrier density in the oxide semiconductor layer is less than 1×

10¹⁷ /cm³.

6. The semiconductor device according to claim 1, wherein a concentration of hydrogen in the oxide semiconductor layer is less than or equal to 2×

10²⁰ atoms/cm³.

7. The semiconductor device according to claim 1, further comprising:

an insulating film in contact with the multi-layer film,

wherein the insulating film contains a peroxide radical, and

wherein a spin density attributed to the peroxide radical is greater than or equal to 5×

10¹⁷ spins/cm³.

8. The semiconductor device according to claim 1,

wherein the protective layer further comprises a third layer under the first layer, and

wherein the third layer comprises silicon oxide or silicon oxynitride,

wherein a spin density in the third layer attributed to a signal with a g factor of 2.001 in ESR is less than or equal to 3×

10′

¹⁷spins/cm³.

9. The semiconductor device according to claim 1,

wherein the gate insulating film comprises aluminum oxide.