Electrode contacts

• US 9,831,462 B2
• Filed: 10/18/2016
• Issued: 11/28/2017
• Est. Priority Date: 12/25/2013
• Status: Active Grant

• Current Assignee: IGNIS Innovation Incorporated
• Original Assignee: IGNIS Innovation Incorporated
• Inventors: Chaji, Gholamreza
• Primary Examiner(s): Yechuri, Sitaramarao S
• Application Number:
  US15/296,424
• Publication Number:
  US 20170040564A1
• Time in Patent Office: 406 Days
• Field of Search: None
• CPC Class Codes: H10K 2102/3026 Top emission
• CPC Class Codes: H10K 50/813 characterised by their shape
• CPC Class Codes: H10K 50/814 combined with auxiliary electrodes, e.g. ITO layer combined with metal lines
• CPC Class Codes: H10K 50/816 Multilayers, e.g. transparent multilayers
• CPC Class Codes: H10K 50/822 characterised by their shape
• CPC Class Codes: H10K 50/824 combined with auxiliary electrodes
• CPC Class Codes: H10K 50/828 Transparent cathodes, e.g. comprising thin metal layers
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 71/60 Forming conductive regions or layers, e.g. electrodes

Abstract

A device structure providing contact to conductive layers via a deep trench structure is disclosed. The device includes a first dielectric layer including a first opening. A first conductive layer is deposited over the first dielectric layer and the first opening. A second dielectric layer is deposited on the first conductive layer. The second dielectric layer includes a second opening. A second conductive layer is deposited over the second dielectric layer and the first and second openings. A semiconductor layer is deposited on the second dielectric layer such that the semiconductor layer is not continuous on at least part of the walls of the first or second openings. A top electrode layer is deposited on the semiconductor layer. The top electrode layer is in contact with the second conductive layer on at least part of the walls of the first or second openings.

Claims

1. A device structure providing contact to conductive layers via a deep trench structure, the device structure comprising:

a first dielectric layer including a first opening, the first opening having walls on the first dielectric layer;

a first conductive layer deposited over the first dielectric layer and the first opening;

a second dielectric layer deposited on the first conductive layer, the second dielectric layer including a second opening having walls on the second dielectric layer;

a second conductive layer deposited over the second dielectric layer and the first and second openings;

a semiconductor layer deposited on the second dielectric layer such that the semiconductor layer is not continuous on at least part of the walls of the first or second openings; and

a top electrode layer deposited directly on the semiconductor layer, the top electrode layer in contact with the second conductive layer only on the at least part of the walls of the first or second openings where the semiconductor layer is not continuous.

2. A device structure providing contact to conductive layers via a deep trench structure, the device structure comprising:

a material structure including at least one flat top surface, each flat top surface around a corresponding opening of at least one opening, each opening having walls on the material structure;

a conductive layer deposited over the material structure and the at least one opening;

a semiconductor layer deposited on the conductive layer, the semiconductor layer being continuous on each of the at least one flat top surface of the material structure, the semiconductor layer continuously covering a lower portion of the walls of each opening, and being discontinuous on an upper portion of the walls of each opening between the lower portion of the walls of each opening and the flat top surface corresponding to the opening; and

a top electrode layer deposited on the semiconductor layer, the top electrode layer in contact with the conductive layer on the upper portion of the walls of each opening and in direct contact with the semiconductor layer on the lower portion of the walls of each opening.

3. The device structure of claim 2, wherein the at least one opening is created by one of lithography, lift off, moulding or shadow masking.

4. The device structure of claim 2, wherein the semiconductor layer is an organic light emitting diode.

5. The device structure of claim 2, wherein the material structure comprises at least one of a silicon-nitride dielectric layer and a polymer dielectric layer.

6. The device structure of claim 2, wherein the material structure comprises at least one layer, and wherein the at least one layer of the material structure, the conductive layer, and the semiconductor layer are deposited via at least one of PECVD, CVD, sputtering, vapor deposition, printing, spin coating, and spray coating.

7. A method of fabricating a device structure providing contact to conductive layers via a deep trench structure, the method comprising:

fabricating a material structure including at least one flat top surface, each flat top surface around a corresponding opening of at least one opening, each opening having walls on the material structure;

depositing a conductive layer over the material structure and the at least one opening;

depositing a semiconductor layer on the conductive layer, the semiconductor layer being continuous on each of the at least one flat top surface of the material structure, the semiconductor layer continuously covering a lower portion of the walls of each opening, and being discontinuous on an upper portion of the walls of each opening between the lower portion of the walls of each opening and the flat top surface corresponding to the opening; and

depositing a top electrode layer deposited on the semiconductor layer, the top electrode layer in contact with the conductive layer on the upper portion of the walls of each opening and in direct contact with the semiconductor layer on the lower portion of the walls of each opening.

8. The method of claim 7, wherein the at least one opening is fabricated at least in part by one of lithography, lift off, moulding or shadow masking.

9. The method of claim 7, wherein the semiconductor layer is an organic light emitting diode.

10. The method of claim 7, wherein the material structure comprises at least one of a silicon-nitride dielectric layer and a polymer dielectric layer.

11. The method of claim 7, wherein the material structure comprises at least one layer, and wherein the at least one layer of the material structure is fabricated at least partly via, and the conductive and semiconductor layers are deposited via at least one of PECVD, CVD, sputtering, vapor deposition, printing, spin coating, and spray coating.