Half bridge driver circuits

• US 9,831,867 B1
• Filed: 02/22/2017
• Issued: 11/28/2017
• Est. Priority Date: 02/22/2016
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel Marvin, Sharma, Santosh, Zhang, Ju, Giandalia, Marco, Ribarich, Thomas
• Primary Examiner(s): Skibinski, Thomas
• Application Number:
  US15/439,785
• Time in Patent Office: 279 Days
• Field of Search: 327108-113, 327333, 327427, 327434, 327437, 326 82, 326 83, 326 87
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1033 Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/1203 Rectifying Diode
• CPC Class Codes: H01L 2924/1304 : Transistor
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H03K 17/26 : Modifications for temporary blocking after receipt of control pulses
• CPC Class Codes: H03K 19/017509 : Interface arrangements
• CPC Class Codes: H03K 2217/0063 : High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 2217/0072 : Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load

Abstract

A half bridge GaN circuit is disclosed. The circuit includes a low side circuit, which has a low side switch, a low side switch driver configured to drive the low side switch, a first level shift circuit configured to receive a first level shift signal, and a second level shift circuit configured to generate a second level shift signal. The half bridge GaN circuit also includes a high side circuit, which has a high side switch configured to be selectively conductive according to a voltage level of a received high side switch signal, and a high side switch driver configured to generate the high side switch signal in response to the level shift signals. A transition in the voltage of the high side switch signal causes the high side switch driver to prevent additional transitions of the voltage level of the high side switch signal for a period of time.

Claims

1. A half bridge GaN circuit, comprising:

a low side circuit, comprising;

a low side switch,

a low side switch driver configured to drive the low side switch,

a first level shift circuit configured to receive a first level shift signal, and

a second level shift circuit configured to generate a second level shift signal; and

a high side circuit, comprising;

a high side switch configured to be selectively conductive according to a voltage level of a received high side switch signal, and

a high side switch driver configured to generate the high side switch signal in response to the first and second level shift signals, wherein a first transition in the voltage of the high side switch signal causes the high side switch driver to prevent additional transitions of the voltage level of the high side switch signal for a period of time.

2. The circuit of claim 1, wherein in response to the first transition in the voltage of the high side switch signal, the high side switch driver is configured to prevent the additional transitions of the voltage level of the high side switch signal for the period of time regardless of transitions in either the first level shift signal or the second level shift signal.

3. The circuit of claim 1, further comprising:

an on signal generator configured to receive the first level shift signal and to generate an on signal based on the first level shift signal;

an off signal generator configured to receive the second level shift signal and to generate an off signal based on the second level shift signal,

wherein the high side switch driver is configured to generate the high side switch signal having a voltage level which causes the high side switch to be conductive in response to the on signal,

wherein the high side switch driver is configured to generate the high side switch signal having a voltage level which causes the high side switch to be non-conductive in response to the off signal.

4. The circuit of claim 3, wherein in response to the first transition in the voltage of the high side switch signal, the high side switch driver is configured to prevent the additional transitions of the voltage level of the high side switch signal by disabling the on signal generator and by disabling the off signal generator.

5. The circuit of claim 3, wherein the first transition in the voltage of the high side switch signal causes the high side switch to become conductive, wherein in response to the first transition in the voltage of the high side switch signal, the high side switch driver is configured to prevent the additional transitions of the voltage level of the high side switch signal by disabling the off signal generator.

6. The circuit of claim 5, wherein a second transition in the voltage of the high side switch signal causes the high side switch to become non-conductive, wherein in response to the second transition in the voltage of the high side switch signal, the high side switch driver is configured to prevent the additional transitions of the voltage level of the high side switch signal by disabling the on signal generator.

7. The circuit of claim 5, wherein a second transition in the voltage of the high side switch signal causes the high side switch to become non-conductive, wherein in response to the second transition in the voltage of the high side switch signal, the high side switch driver is configured to not prevent the additional transitions of the voltage level of the high side switch signal.

8. The circuit of claim 3, wherein the first transition in the voltage of the high side switch signal causes the high side switch to become non-conductive, wherein in response to the first transition in the voltage of the high side switch signal, the high side switch driver is configured to prevent the additional transitions of the voltage level of the high side switch signal by disabling the on signal generator.

9. The circuit of claim 3, wherein the first transition in the voltage of the high side switch signal causes the high side switch to become non-conductive, wherein in response to the first transition in the voltage of the high side switch signal, the high side switch driver is configured to prevent the additional transitions of the voltage level of the high side switch signal by disabling the on signal generator and by disabling the off signal generator.

10. The circuit of claim 9, wherein a second transition in the voltage of the high side switch signal causes the high side switch to become conductive, wherein in response to the second transition in the voltage of the high side switch signal, the high side switch driver is configured to prevent the additional transitions of the voltage level of the high side switch signal by disabling the off signal generator.

11. The circuit of claim 1, wherein the duration of the period of time is determined by a duration of a pulse generated by a pulse generator.

12. The circuit of claim 11, wherein the pulse generator is configured to terminate the pulse in response to a terminate signal generated in response to the first transition.

13. A half bridge GaN circuit, comprising:

a low side circuit, comprising;

a low side switch,

a low side switch driver configured to drive the low side switch,

a first level shift circuit configured to receive a first level shift signal, and

a second level shift circuit configured to generate a second level shift signal; and

a high side circuit, comprising;

a high side switch configured to be selectively conductive according to a voltage level of a received high side switch signal, and

a high side switch driver configured to generate the high side switch signal in response to the first and second level shift signals, wherein a first transition in the voltage of the high side switch signal causes the high side switch driver to generate a first signal, wherein the first signal initiates a time period during which additional transitions in the voltage level of the high side switch signal are prevented, and wherein the first transition in the voltage of the high side switch signal causes the high side switch driver to generate a second signal, wherein the second signal terminates the time period.

14. The circuit of claim 13, wherein in response to the first transition in the voltage of the high side switch signal, the high side switch driver is configured to prevent the additional transitions of the voltage level of the high side switch signal for the period of time regardless of transitions in either the first level shift signal or the second level shift signal.

15. The circuit of claim 13, further comprising:

an on signal generator configured to receive the first level shift signal and to generate an on signal based on the first level shift signal;

an off signal generator configured to receive the second level shift signal and to generate an off signal based on the second level shift signal,

wherein the high side switch driver is configured to generate the high side switch signal having a voltage level which causes the high side switch to be conductive in response to the on signal,

wherein the high side switch driver is configured to generate the high side switch signal having a voltage level which causes the high side switch to be non-conductive in response to the off signal.

16. The circuit of claim 15, wherein in response to the first transition in the voltage of the high side switch signal, the high side switch driver is configured to prevent the additional transitions of the voltage level of the high side switch signal by disabling the on signal generator and by disabling the off signal generator.

17. The circuit of claim 15, wherein the first transition in the voltage of the high side switch signal causes the high side switch to become conductive, wherein in response to the first transition in the voltage of the high side switch signal, the high side switch driver is configured to prevent the additional transitions of the voltage level of the high side switch signal by disabling the off signal generator.

18. The circuit of claim 17, wherein a second transition in the voltage of the high side switch signal causes the high side switch to become non-conductive, wherein in response to the second transition in the voltage of the high side switch signal, the high side switch driver is configured to prevent the additional transitions of the voltage level of the high side switch signal by disabling the on signal generator.

19. The circuit of claim 17, wherein a second transition in the voltage of the high side switch signal causes the high side switch to become non-conductive, wherein in response to the second transition in the voltage of the high side switch signal, the high side switch driver is configured to not prevent the additional transitions of the voltage level of the high side switch signal.

20. The circuit of claim 15, wherein the first transition in the voltage of the high side switch signal causes the high side switch to become non-conductive, wherein in response to the first transition in the voltage of the high side switch signal, the high side switch driver is configured to prevent the additional transitions of the voltage level of the high side switch signal by disabling the on signal generator.

21. The circuit of claim 15, wherein the first transition in the voltage of the high side switch signal causes the high side switch to become non-conductive, wherein in response to the first transition in the voltage of the high side switch signal, the high side switch driver is configured to prevent the additional transitions of the voltage level of the high side switch signal by disabling the on signal generator and by disabling the off signal generator.

22. The circuit of claim 21, wherein a second transition in the voltage of the high side switch signal causes the high side switch to become conductive, wherein in response to the second transition in the voltage of the high side switch signal, the high side switch driver is configured to prevent the additional transitions of the voltage level of the high side switch signal by disabling the off signal generator.