Array substrate, manufacturing method thereof and display device

• US 9,835,921 B2
• Filed: 09/18/2014
• Issued: 12/05/2017
• Est. Priority Date: 05/26/2014
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Cao, Zhanfeng, Ding, Luke, Zhang, Wenlin, Kong, Xiangchun, Zhang, Feng, Yao, Qi, Zhang, Zhixing
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US14/436,004
• Publication Number:
  US 20170139246A1
• Time in Patent Office: 1,174 Days
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/13439 characterised by their electrical, optical, physical properties; materials therefor; method of making
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136222 Colour filters incorporated in the active matrix substrate
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/121 common or background
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/78633 with a light shield

Abstract

An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate comprises a plurality of pixel unit regions each including a thin-film transistor (TFTs) and a pixel electrode. A first insulating layer provided with a first through hole and a second through hole is formed between an active layer of the TFT and the pixel electrode. A source electrode of the TFT is connected with the active layer through the first through hole. A drain electrode of the TFT is lapped onto the pixel electrode and connected with the active layer through the second through hole. The array substrate can prevent the oxidization of metal such as copper in the process of patterning a transparent conductive film.

Claims

1. An array substrate comprising:

a plurality of pixel unit regions arranged in an array,

wherein each of the pixel unit regions includes;

a thin-film transistor (TFT) and a pixel electrode;

a first insulating layer is interposed between an active layer of the TFT and the pixel electrode and provided with a first through hole and a second through hole which respectively correspond to both ends of the active layer;

a source electrode of the TFT is connected with the active layer through the first through hole; and

a drain electrode of the TFT is lapped with the pixel electrode and connected with the active layer through the second through hole, and

wherein the pixel electrode is interposed between the drain electrode and the active layer.

2. The array substrate according to claim 1, further comprising:

data lines, wherein the data lines and the source electrodes and the drain electrodes of the TFTs are disposed on the same layer.

3. The array substrate according to claim 2, further comprising:

a second insulating layer and a common electrode disposed above the pixel electrodes in sequence.

4. The array substrate according to claim 2, further comprising:

a second insulating layer and a common electrode disposed below the TFTs in sequence.

5. The array substrate according to claim 2, further comprising:

black matrices and color filters arranged corresponding to the pixel unit regions.

6. The array substrate according to claim 1, further comprising:

a second insulating layer and a common electrode disposed above the pixel electrodes in sequence.

7. The array substrate according to claim 6, further comprising:

black matrices and color filters arranged corresponding to the pixel unit regions.

8. The array substrate according to claim 1, further comprising:

a second insulating layer and a common electrode disposed below the TFTs in sequence.

9. The array substrate according to claim 8, further comprising:

black matrices and color filters arranged corresponding to the pixel unit regions.

10. The array substrate according to claim 1, further comprising:

black matrices and color filters arranged corresponding to the pixel unit regions.

11. A display device, comprising the array substrate according to claim 1.

12. The array substrate according to claim 1, wherein the pixel electrode is formed with through holes respectively at the first through hole and the second through hole.

13. A method for manufacturing an array substrate, comprising:

forming patterns of an active layer of a thin film transistor (TFT), a first insulating layer and a pixel electrode, in which the first insulating layer is provided with a first through hole and a second through hole which respectively correspond to both ends of the active layer; and

forming patterns of a source electrode and a drain electrode of the TFT, in which the source electrode of the TFT is connected with the active layer through the first through hole and the drain electrode of the TFT is lapped with the pixel electrode and connected with the active layer through the second through hole,

wherein the pixel electrode is interposed between the drain electrode and the active layer.

14. The method according to claim 13, wherein forming of the patterns of the active layer of the TFT, the first insulating layer and the pixel electrode includes:

forming a pattern of the active layer;

forming the first insulating layer and a transparent conductive film;

patterning the first insulating layer and the transparent conductive films;

forming the first through hole and the second through hole of the first insulating layer; and

forming the pixel electrode.

15. The method according to claim 14, wherein forming of the patterns of the source electrode and the drain electrode of the TFT includes:

forming a data line and the patterns of the source electrode and the drain electrode of the TFT.

16. The method according to claim 14, further comprising:

forming a second insulating layer and a common electrode, wherein the second insulating layer is disposed between the pixel electrode and the common electrode.

17. The method according to claim 13, wherein forming of the patterns of the source electrode and the drain electrode of the TFT includes:

forming a data line and the patterns of the source electrode and the drain electrode of the TFT.

18. The method according to claim 17, further comprising:

forming a second insulating layer and a common electrode, wherein the second insulating layer is disposed between the pixel electrode and the common electrode.

19. The method according to claim 13, further comprising:

forming a second insulating layer and a common electrode, wherein the second insulating layer is disposed between the pixel electrode and the common electrode.

20. The method according to claim 13, wherein the source electrode and the drain electrode are formed after the pixel electrode.