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Configurable high speed FPGA scan mechanism controller

  • US 9,836,221 B1
  • Filed: 11/10/2015
  • Issued: 12/05/2017
  • Est. Priority Date: 11/10/2014
  • Status: Active Grant
First Claim
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1. A method for controlling a physical system, comprising:

  • receiving an input signal at an input port, wherein the input signal represents a first system parameter;

    storing the input signal at a first address in a memory;

    providing the input signal from the first address in the memory as an operand to a first functional block of a field programmable gate array (FPGA), wherein the first functional block generates at least a first intermediate output value, wherein the first functional block is determined by a state machine, and wherein the input signal is provided from the first address in the memory to the first functional block over a first programmable interconnect;

    storing the first intermediate output value in a second address in the memory, wherein the second address in the memory is determined by the state machine, and wherein the first intermediate output value is provided from the first functional block to the second address in the memory over a second programmable interconnect;

    providing the first intermediate output value from the second address in the memory as an operand to a second functional block of the FPGA, wherein the second functional block generates at least a second intermediate output value, wherein the second functional block is determined by the state machine, and wherein the first intermediate output is provided from the second address in the memory to the second functional block over a third programmable interconnect;

    storing the second intermediate output value in a third address in the memory, wherein the third address in the memory is determined by the state machine, and wherein the second intermediate output value is provided from the second functional block to the third address in the memory over a fourth programmable interconnect; and

    providing a final output value from the memory to an output port.

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