Method and system for accessing a flash memory device

• US 9,836,227 B2
• Filed: 09/22/2016
• Issued: 12/05/2017
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki, Pyeon, Hong Beom
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US15/273,122
• Publication Number:
  US 20170109059A1
• Time in Patent Office: 439 Days
• Field of Search: 36518511, 36518523, 36518533, 36518904, 36518915, 36518916, 365219, 36523003, 36523005
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 8/10 Decoders

Abstract

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Claims

1. A flash memory system comprising:

at least one flash memory device, each flash memory device comprising;

a plurality of memory banks configured to perform operations concurrently to each other, each memory bank comprising a separate row decoder and a separate page buffer;

a chip select input configured to activate the plurality of memory banks for the respective flash memory device;

a status register for each memory bank, each status register configured to indicate whether the respective memory bank is busy; and

a plurality of interfaces, each interface configured to receive data streams from a memory controller, each data stream comprising the command data, address data, and write data receivable at different times; and

the memory controller communicatively coupled to the at least one flash memory device and configured to select any one of the plurality of interfaces of the at least one flash memory device in order to provide data streams to the selected interface.

2. The flash memory system of claim 1, wherein the status register for each respective memory bank further updates the status of the respective memory bank by clearing a bit value in the status register to indicate that the respective memory bank is ready when routing of write data to a memory cell array of the respective memory bank is completed.

3. The flash memory system of claim 1, wherein each of the at least one flash memory device further comprises an addressing circuitry configured to parse a data stream to extract a memory bank identifier of the respective flash memory device.

4. The flash memory system of claim 3, wherein the status register for each respective memory bank responds to a read status request from the memory controller when the memory bank identifier of the respective memory bank is extracted from the read status request, status data being stored in the status register of the respective memory bank.

5. The flash memory system of claim 1, wherein each of the at least one flash memory device further comprises a control module configured to route write data of a data stream between the selected interface and any one of the plurality of memory banks for the respective flash memory device.

6. A flash memory device, comprising:

a plurality of memory banks configured to perform operations concurrently to each other, each memory bank comprising a separate row decoder and a separate page buffer;

a chip select input configured to activate the plurality of memory banks for the flash memory device;

a status register for each memory bank, each status register configured to indicate whether the respective memory bank is busy; and

a plurality of interfaces, each interface configured to receive data streams from a memory controller, each data stream comprising command data, address data, and write data receivable at different times, the address data comprising a memory bank identifier to address any one of the plurality of memory banks.

7. The flash memory device of claim 6, wherein the status register for each respective memory bank further updates the status of the respective memory bank by clearing a bit value in the status register to indicate that the respective memory bank is ready when routing of write data to a memory cell array of the respective memory bank is completed.

8. The flash memory device of claim 6, further comprising an addressing circuitry configured to parse a data stream to extract the memory bank identifier of the flash memory device.

9. The flash memory device of claim 8, wherein the status register for each respective memory bank responds to a read status request from the memory controller when the memory bank identifier of the respective memory bank is extracted from the read status request, status data being stored in the status register of the respective memory bank.

10. The flash memory device of claim 6, wherein the flash memory device further comprises a control module configured to route write data of a data stream between any one of the plurality of interfaces and a memory cell array of any one of the plurality of memory banks.