Non-volatile RAM and flash memory in a non-volatile solid-state storage

• US 9,836,245 B2
• Filed: 07/02/2014
• Issued: 12/05/2017
• Est. Priority Date: 07/02/2014
• Status: Active Grant

• Current Assignee: Pure Storage, Inc.
• Original Assignee: Pure Storage, Inc.
• Inventors: Hayes, John, Gupta, Shantanu, Davis, John, Gold, Brian, Tan, Zhangxi
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): ROCHE, JOHN B
• Application Number:
  US14/322,891
• Publication Number:
  US 20160004452A1
• Time in Patent Office: 1,252 Days
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A non-volatile solid-state storage is provided. The non-volatile solid state storage includes a non-volatile random access memory (NVRAM) addressable by a processor external to the non-volatile solid state storage. The NVRAM is configured to store user data and metadata relating to the user data. The non-volatile solid state storage includes a flash memory addressable by the processor. The flash memory is configured to store the user data responsive to the processor directing transfer of the user data from the NVRAM to the flash memory.

Claims

1. A non-volatile solid-state storage, comprising:

a non-volatile random access memory (NVRAM) addressable by a first controller internal to the non-volatile solid-state storage, and by a second controller external to the non-volatile solid-state storage, the NVRAM configurable to store user data and metadata relating to the user data;

a flash memory, addressable by the first controller and by the second controller; and

the first controller configurable to cooperate with further non-volatile solid-state storage as a storage cluster, the storage cluster having a plurality of storage nodes and a plurality of authorities associated with the plurality of storage nodes, the plurality of storage nodes configurable to write data segments across the non-volatile solid-state storage, with each data segment associated with one of the plurality of authorities and each authority associated with a storage node of the storage cluster such that for each data segment, as a logical container of data, a segment identifier determines which of the plurality of authorities reads or writes the data segment and points to storage nodes for data striping for the data segment.

2. The non-volatile solid-state storage of claim 1, further comprising:

a direct memory access (DMA) engine, configured to move the user data from the NVRAM to the flash memory and to perform a cyclic redundancy check (CRC) to verify the user data.

3. The non-volatile solid-state storage of claim 1, wherein:

the NVRAM is configurable as a workspace for the second controller to apply the metadata.

4. The non-volatile solid-state storage of claim 1, further comprising:

a direct memory access (DMA) engine, configured to transfer the user data from the NVRAM to the flash memory responsive to a plurality of writes of the user data to the NVRAM providing sufficient user data in the NVRAM for a page write to the flash memory.

5. The non-volatile solid-state storage of claim 1, wherein:

the NVRAM includes dynamic random access memory (DRAM) and is powered by an energy reserve during power loss operation.

6. The non-volatile solid-state storage of claim 1, wherein the non-volatile solid state storage is contained within a storage node of the storage cluster, the storage cluster comprising the plurality of storage nodes wherein each of the plurality of storage nodes has one or more of the plurality of authorities, each of which directs sharding and reassembling of a range of the user data belonging to the respective authority.

7. The non-volatile solid-state storage of claim 6, wherein the plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data, via erasure coding, with a failure of two of the plurality of storage nodes.

8. A storage cluster, comprising:

a plurality of storage nodes configured to stripe data segments across the plurality of storage nodes, with each data segment associated with an authority and each authority associated with a storage node such that for each data segment, as a logical container of data, a segment identifier determines which of a plurality of such authorities reads or writes the data segment and points to storage nodes for data striping for the data segment, each of the plurality of storage nodes having nonvolatile solid-state memory for storage of user data, the nonvolatile solid-state memory comprising;

a non-volatile random access memory (NVRAM) configured to receive the user data and metadata from a processor of a storage node of the plurality of storage nodes, the NVRAM addressable by the processor;

a flash memory addressable by the processor; and

a controller configured to manage the user data in the flash memory, wherein the NVRAM and the flash memory are addressable by the controller.

9. The storage cluster of claim 8, further comprising:

an energy reserve coupled to the NVRAM and the flash memory, the energy reserve having sufficient capacity to support transfer of contents of the NVRAM to the flash memory; and

a direct memory access (DMA) unit configured to transfer the contents of the NVRAM to the flash memory, responsive to power loss.

10. The storage cluster of claim 8, wherein:

the metadata is not transferred from the NVRAM to the flash memory except in the event of the power loss; and

a DMA unit configured to transfer the metadata from the NVRAM to the flash memory in the event of power loss.

11. The storage cluster of claim 8, further comprising:

the controller configured to manage an address translation table that maps from a first address space to a second address space.

12. The storage cluster of claim 8, wherein the metadata pertains to sharding and reassembling the user data as performed by the processor, and wherein each of the plurality of storage nodes has one or more respective authorities, each of which directs the sharding and the reassembling of a range of the user data belonging to the respective authority.

13. The storage cluster of claim 8, wherein:

the flash memory is configured to receive the user data from the NVRAM as a page write; and

the NVRAM is configured to receive the user data from the processor with each write to the NVRAM having a smaller amount of data than the page write to the flash memory.

14. The storage cluster of claim 8, wherein the plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data, via erasure coding, with a failure of two of the plurality of storage nodes.

15. A method of accessing a non-volatile solid-state storage, performed by a storage system, comprising:

writing user data into a storage cluster having a plurality of storage nodes, the user data written as data segments across non-volatile random-access memory (NVRAM) of a plurality of non-volatile solid-state storage units of the storage cluster, with each data segment associated with an authority and each authority associated with a storage node such that for each data segment, as a logical container of data, a segment identifier determines which of a plurality of such authorities reads or writes the data segment and points to storage nodes for data striping for the data segment; and

writing the user data from the NVRAM to a flash memory of a non-volatile solid-state storage unit, wherein each of the NVRAM and the flash memory is addressable as a distinct resource by a processor of the storage node, wherein each of the NVRAM and the flash memory is addressable as the distinct resource by a controller of the non-volatile solid-state storage unit, and wherein the writing the user data from the NVRAM to the flash memory of the non-volatile solid-state storage unit is directed by the processor of the storage node.

16. The method of claim 15, further comprising:

writing an update of the user data to the NVRAM, wherein the update obsoletes a portion of the user data in the NVRAM, and wherein the writing the user data from the NVRAM to the flash memory is performed in a batch mode transfer that includes the update of the user data.

17. The method of claim 15, wherein the storage node has one or more authorities, each of which directs sharding and reassembling of a range of the user data belonging to the respective authority.

18. The method of claim 15, further comprising:

acknowledging a client write of the user data, responsive to the writing the user data to the NVRAM, the acknowledging occurring prior to the writing the user data from the NVRAM to the flash memory.

19. The method of claim 15, further comprising:

collecting a plurality of writes of the user data to the NVRAM, prior to the writing the user data from the NVRAM to the flash memory.

20. The method of claim 15, further comprising:

searching in the flash memory for information stored in a subset of a flash page, wherein the searching is performed by the controller of the non-volatile solid-state storage unit; and

sending the information to the processor of the storage node without sending an entirety of the flash page to the processor of the storage node.