Parallelizing boot operations

• US 9,836,306 B2
• Filed: 06/25/2014
• Issued: 12/05/2017
• Est. Priority Date: 07/31/2013
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Baratam, Vamsi Krishna, Aytek, Tolga Nihat
• Primary Examiner(s): Huynh, Kim
• Assistant Examiner(s): Chan, Danny
• Application Number:
  US14/315,019
• Publication Number:
  US 20150039876A1
• Time in Patent Office: 1,259 Days
• Field of Search: None
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

The present disclosure describes apparatuses and techniques for parallelizing boot operations. In some aspects, an operation transferring a boot image from a non-volatile memory to a volatile memory is initiated prior to completion an operation validating another boot image previously-transferred into the volatile memory. This can be effective to enable transfer operations and validation operations of boot images to be performed in parallel. By so doing, delays between the transfer and validation operations can be minimized thereby reducing device boot times.

Claims

1. A method comprising:

executing, responsive to receiving a packed command from a host driver implemented by a processor of a host device, the packed command effective to initiate reading of multiple boot images that are stored in a first memory of a memory device;

initiating, via a direct memory access (DMA) controller of the memory device and based on a first transfer descriptor of a set of transfer descriptors stored in a second memory of the host device, a first DMA transfer operation transferring a first boot image of the multiple boot images from the first memory of the memory device into the second memory of the host device, the first transfer descriptor configured to cause an interrupt responsive to completion of the first DMA transfer operation;

causing, via the interrupt and after completion of the first DMA transfer operation, initiation of a first validation operation by the processor of the host device to validate the first boot image in the second memory of the host device effective to verify that the first boot image is secure; and

initiating, via the DMA controller of the memory device, without waiting for completion of the first validation operation, and based on a second transfer descriptor of the set of transfer descriptors stored in the second memory of the host device, subsequent DMA transfer operations transferring at least a second boot image of the multiple boot images from the first memory of the memory device into the second memory of the host device, at least a portion of the subsequent DMA transfer operations occurring while the processor of the host device performs the first validation operation of the first boot image in the second memory of the host device.

2. The method as recited in claim 1, further comprising

transferring, after completion of the first validation operation and validation operations for others of the multiple boot images, control to one of the multiple boot images.

3. The method as recited in claim 1, wherein the first validation operation comprises calculating a hash value for the first boot image and comparing the hash value with a predetermined reference value.

4. The method as recited in claim 1, wherein the first memory of the memory device includes a Flash memory and the second memory of the host device is a random-access memory (RAM).

5. The method as recited in claim 4, wherein the Flash memory comprises one of a serial peripheral interface (SPI) Flash memory, NAND Flash memory, embedded Flash memory, or a Flash memory of an embedded multimedia card (eMMC) device.

6. The method as recited in claim 1, wherein the multiple boot images are located in a same partition of the first memory of the memory device.

7. The method as recited in claim 1, wherein the memory device comprises an embedded multimedia card (eMMC) device.

8. The method as recited in claim 1, wherein the packed command enables the multiple boot images to be read from the first memory of the memory device without issuing individual read commands for each of the multiple boot images.

9. A method comprising:

retrieving, in response to a start of a boot sequence and via a processor of a host device, a header image from a non-volatile memory of a memory device, the header image describing multiple boot images stored in the non-volatile memory;

constructing, based on the header image and in a volatile memory of a host device, a packed command describing respective locations of the multiple boot images stored in the non-volatile memory of the memory device;

constructing, based on the header image and in the volatile memory of the host device, direct memory access (DMA) descriptors describing respective destination locations of the multiple boot images in the volatile memory of the host device, at least some of the DMA descriptors configured to cause an interrupt responsive to completing a DMA transfer of one of the multiple boot images as specified by the DMA descriptor; and

issuing the packed command to a memory controller of the memory device effective to cause the memory controller to;

initiate, via a DMA engine of the memory device and based on the DMA descriptors in the volatile memory of the host device, respective DMA transfers of the multiple boot images from the non-volatile memory of the memory device to the volatile memory of the host device; and

cause, via the interrupts caused by the DMA descriptors responsive to completing transfers of the multiple boot images into volatile memory of the host device, the processor of the host device to initiate respective validation operations of the multiple boot images, at least one of the respective DMA transfers transferring one of the multiple boot images while the processor of the host device validates a previously-transferred one of the multiple boot images.

10. The method as recited in claim 9, wherein the non-volatile memory is Flash memory and the packed command describes respective sizes of the multiple boot images and respective addresses of the multiple boot images in the Flash memory.

11. The method as recited in claim 9, wherein:

at least two of the DMA descriptors are configured as a chain of DMA descriptors;

the at least two of the DMA descriptors are associated with transferring one of the multiple boot images; and

a last DMA descriptor in the chain of DMA descriptors is configured to trigger an interrupt that indicates complete transfer of the one of the multiple boot images.

12. A System-on-Chip (SoC) comprising:

a processor configured to implement validation operations and other functionalities of a device;

a volatile memory configured to receive the multiple boot images;

an interface to a memory device that includes;

(i) non-volatile memory configured to store multiple boot images; and

(ii) a direct memory access (DMA) controller configured to enable access between the volatile memory of the SoC and the non-volatile memory of the memory device; and

a boot manager configured to;

access a header image stored in the non-volatile memory of the memory device;

interpret the header image to provide information describing respective sizes of the multiple boot images, or locations of the multiple boot images in the non-volatile memory, and destination locations for the multiple boot images in the volatile memory;

construct, based on the header image, packed commands that specify the respective sizes of the multiple boot images and the locations of the multiple boot images in the non-volatile memory;

construct, based on the header image, transfer descriptors that each specify a size of one of the multiple boot images and the destination location of the boot image in the volatile memory, the transfer descriptors including information that describes a DMA interrupt action associated with transferring each of the multiple boot images;

issue the packed commands to the memory device effective to initiate reading of the multiple boot images from the non-volatile memory of the memory device;

initiate, via the DMA controller and based on a first of the transfer descriptors, a first DMA transfer operation transferring a first of the multiple boot images from the non-volatile memory to the volatile memory;

cause, in response to the first transfer descriptor triggering a first DMA interrupt indicating completion of the first DMA transfer operation of the first boot image to the volatile memory, the processor to initiate a validation operation to validate the first boot image in the volatile memory; and

initiate, via the DMA controller, based on a second of the transfer descriptors, and without waiting for completion of the validation operation of the first boot image, a second DMA transfer operation transferring a second of the multiple boot images from the non-volatile memory to the volatile memory, at least a portion of the second boot image being transferred via the second DMA transfer while the processor performs the validation operation to validate the first boot image in the volatile memory.

13. The System-on-Chip as recited in claim 12, wherein the validation operation is a first validation operation and the boot manager is further configured to:

cause, in response to the second transfer descriptor triggering a second DMA interrupt indicating completion of the second DMA transfer operation, the processor to initiate a second validation operation to validate the second boot image in the volatile memory; and

transfer, after completion of the second validation operation, control of the device to the first boot image or the second boot image.

14. The System-on-Chip as recited in claim 12, wherein the boot manager is further configured to construct advanced DMA (ADMA) descriptors based on the information provided by the header image and cause the DMA controller to perform, based on the ADMA descriptors, the first and second DMA transfer operations.

15. The System-on-Chip as recited in claim 12, wherein the respective DMA transfer operations transfer the first and second boot images over an Advanced eXtensible Interface (AXI) bus, Advanced High Performance Bus (AHB), or Open Core Protocol (OCP) bus.

16. The System-on-Chip as recited in claim 12, wherein the DMA controller operates in compliance with version 4.5 of the Joint Electron Device Engineering Council (JEDEC) Embedded Multimedia Card (eMMC) standard.

17. The System-on-Chip as recited in claim 12, wherein the multiple boot images are stored in a same partition of the non-volatile memory.

18. The System-on-Chip as recited in claim 12, wherein the transfer descriptors are configured to cause the DMA controller to treat the respective DMA transfer operations of the first and second boot images as a single transfer.

19. The System-on-Chip as recited in claim 12, wherein the memory device comprises an embedded multimedia card (eMMC) device.

20. The System-on-Chip as recited in claim 12, wherein the packed commands reduce command overhead over the interface by enabling the multiple boot images to be read from the non-volatile memory of the memory device without issuing individual read commands for each of the multiple boot images.