Bridge configuration in computing devices

• US 9,836,417 B2
• Filed: 06/11/2015
• Issued: 12/05/2017
• Est. Priority Date: 04/20/2015
• Status: Active Grant

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: McCabe, Timothy J., Klett, Michael F., Barnes, Edwin D.
• Primary Examiner(s): Patel, Nimesh G
• Application Number:
  US14/737,307
• Publication Number:
  US 20160306757A1
• Time in Patent Office: 908 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 8/63 Image based installation; Cloning; Build to order
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57

Abstract

Systems and methods are disclosed for configuring an interface bridge. A computing system includes a device controller, an interface bridge module coupled to the device controller configured to provide bridge functionality according to a first communication standard, a primary communication interface conforming to the first communication standard and coupled to the interface bridge module. The computing system further includes a first non-volatile memory module coupled to the interface bridge module, the first non-volatile memory module storing first stage boot loader code, a second non-volatile memory module coupled to the device controller, and a secondary communication interface conforming to a second communication standard coupled to the device controller. The device controller is configured to receive update package data over the secondary communication interface, the update package data including a firmware image, and write the update package data to the second non-volatile memory module.

Claims

1. A computing system comprising:

a device controller;

an interface bridge module communicatively coupled to the device controller and configured to provide bridge functionality;

a primary communication interface conforming to a first communication standard and communicatively coupled to the interface bridge module;

a first non-volatile memory module communicatively coupled to the interface bridge module, the first non-volatile memory module storing first stage boot loader code;

a second non-volatile memory module separate from the first non-volatile memory module and communicatively coupled to the device controller; and

a secondary communication interface conforming to a second communication standard and communicatively coupled to the device controller;

wherein the device controller is configured to, while the interface bridge module is held in reset;

receive update package data over the secondary communication interface, the update package data including a firmware image; and

write the update package data to the second non-volatile memory module.

2. The computing system of claim 1, wherein the second communication interface is a serial interface.

3. The computing system of claim 1, wherein the update package data comprises:

second stage boot loader code; and

configuration data for configuring the interface bridge module.

4. The computing system of claim 1, wherein the device controller is further configured to:

hold the secondary communication interface in reset;

activate the primary communication interface;

copy second stage boot loader code of the update package data from the second non-volatile memory module to a volatile memory module; and

execute the second stage boot loader code from the volatile memory module.

5. The computing system of claim 4, wherein the second stage boot loader code, when executed by the device controller, causes the device controller to:

validate configuration data of the update package data;

apply the configuration data to configure the interface bridge module;

validate the firmware image; and

store the firmware image in the first non-volatile memory module.

6. The computing system of claim 1, further comprising a printed circuit board (PCB), wherein the device controller, interface bridge module, and first non-volatile memory module each comprise one or more chips mounted on the PCB.

7. The computing system of claim 1, wherein the first stage boot loader code, when executed by the device controller, causes the device controller to:

initialize the interface bridge module;

spin-up a magnetic disk of the second non-volatile memory module; and

validate second stage boot loader code of the update package data stored in the second non-volatile memory module.

8. The computing system of claim 1, wherein the first stage boot loader code is less than 20 kB in size.

9. The computing system of claim 1, wherein the secondary communication interface is a Serial Input/Output (SIO) interface.

10. The computing system of claim 1, wherein the second non-volatile memory module comprises magnetic memory.

11. The computing system of claim 1, wherein the first non-volatile memory module is a Serial Peripheral Interface (SPI) flash memory module.

12. A method of programming firmware in a computing system, the method comprising:

while holding an interface bridge module coupled to a primary communication interface in reset;

receiving update package data over a secondary communication interface, the update package data comprising second stage boot loader code and a firmware image; and

writing the update package data to a first non-volatile memory module;

loading first stage boot loader code from a second non-volatile memory module to a volatile memory module, the second non-volatile memory module being separate from the first non-volatile memory module and communicatively coupled to the interface bridge module;

executing the first stage boot loader code to;

initialize the interface bridge module; and

copy the update package data from the first non-volatile memory module to the volatile memory module; and

executing the second stage boot loader code to copy the firmware image of the update package data from the volatile memory module to the second non-volatile memory module.

13. The method of claim 12, wherein the method is at least partially performed within an environment-controlled chamber.

14. The method of claim 12, wherein the update package data comprises configuration data for configuring the interface bridge module.

15. The method of claim 12, further comprising activating the primary communication interface after said writing the update package data to the first non-volatile memory module and before said executing the first stage boot loader code.

16. The method of claim 15, wherein executing the second stage boot loader code comprises:

validating configuration data of the update package data;

applying the configuration data; and

validating the firmware image.

17. The method of claim 12, wherein the method is performed at least in part by a device controller mounted to a printed circuit board (PCB), wherein the interface bridge module and first non-volatile memory module each comprise one or more chips mounted to the PCB.

18. The method of claim 12, wherein said executing the first stage boot loader code further comprises:

spinning-up a magnetic disk of the first non-volatile memory module; and

validating the second stage boot loader code.

19. The method of claim 12, wherein the primary communication interface is a Universal Serial Bus (USB) interface.