General input/output architecture, protocol and related methods to implement flow control

• US 9,836,424 B2
• Filed: 12/30/2013
• Issued: 12/05/2017
• Est. Priority Date: 08/24/2001
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ajanovic, Jasmin, Harriman, David, Fanning, Blaise, Lee, David
• Primary Examiner(s): Baturay, Alicia
• Application Number:
  US14/144,309
• Publication Number:
  US 20140115219A1
• Time in Patent Office: 1,436 Days
• Field of Search: 709234
• CPC Class Codes: A47K 7/028 having a rigid handle A47K7/026 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4273 using a clocked protocol
• CPC Class Codes: G06F 2213/0026 PCI express

Abstract

An enhanced general input/output communication architecture, protocol and related methods are presented.

Claims

1. An apparatus, comprising:

a protocol stack including layers to communicate data over a point to point interconnect, wherein the protocol stack including layers comprises a physical layer, a data link layer, and at least one layer higher than the physical layer and data link layer to generate packets corresponding to transactions over the interconnect;

a transmitter block to transmit data on the interconnect;

a first register associated with the transmitter block to store a value comprising a number of credits allocated to the transmitter by a remote receiver;

a second register is to store a value comprising a number of the allocated credits used by the transmitter block;

a receiver block to receive data from a remote transmitter; and

a third register associated with the receiver block to hold a value to represent a total number of credits allocated to the remote transmitter by the receiver block,

wherein the data link layer provides flow control based on the credits and provides error detection based on a checksum added to packets generated in the other layer.

2. The apparatus of claim 1, wherein the transmitter is to determine when a remote receiver is temporarily unable to receive more content according to the number of credits allocated indicated in the first register.

3. The apparatus of claim 1, wherein the first register, second register, and the at least one register of the receiver has a storage capacity of 8 bits.

4. The apparatus of claim 1, wherein the first register, second register, and the at least one register of the receiver are to store the number of credits received, the number of credits used, and the number of credits sent, respectively, modulo 256.

5. The apparatus of 1, wherein the data link layer data comprises a data link layer message.

6. The apparatus of claim 5, wherein the numbers of credits received in the first register and the second register are set to zero upon reset or power-up.

7. A method, comprising:

utilizing a protocol stack including layers to communicate over a point to point interconnect, wherein the protocol stack includes layers comprising a physical layer, a data link layer, and at least one layer higher than the physical layer and data link layer to generate packets corresponding to transactions over the interconnect;

sending data link layer data to a remote transmitter indicating an amount of credits allocated to the remote transmitter;

utilizing a first register associated with a local transmitter to store a value indicating a number of credits allocated to the local transmitter by a remote;

utilizing a second register associated with the local transmitter to store a value indicating a total number of the allocated credits used by the local transmitter;

utilizing the local transmitter to transmit data on the point to point interconnect to the remote receiver; and

utilizing a third register to hold a value to represent a total number of credits allocated to the remote transmitter by a local receiver,

wherein the data link layer provides flow control based on the credits and provides error detection based on a checksum added to packets generated in the other layer.

8. The method of claim 7 further comprising utilizing a remote receiver to transmit information about a current memory space availability to store data in the transmitter.

9. The method of claim 7 further comprising resetting the number of credits received and credits used in the first and second registers to zero upon power-up or reset.

10. The method of claim 7 further comprising refraining from sending packets from the transmitter to the receiver when the value in the first register is equal to zero.

11. The method of claim 10 further comprising utilizing the first register to control the speed of data transfer from the transmitter to a receiver in a remote device.

12. A non-transitory computer readable medium storing computer readable instructions for machine execution of a method comprising:

utilizing a protocol stack including layers to communicate data over a point to point interconnect, wherein the protocol stack including layers comprises a physical layer, a data link layer, and at least one layer higher than the physical layer and data link layer to generate packets corresponding to transactions over the interconnect;

utilizing a transmitter to transmit data on the point to point interconnect;

utilizing a first register associated with the transmitter to store a value comprising a number of credits allocated to the transmitter by a remote receiver;

utilizing a second register to store a value comprising a number of the allocated credits used by the transmitter;

utilizing a receiver to receive data from a remote transmitter;

utilizing a third register associated with the receiver to hold a value to represent a total number of credits allocated to the remote transmitter by the receiver;

utilizing the data link layer to provide flow control for the interconnect based on the credits; and

utilizing the data link layer to provide error detection based on a checksum added to packets generated in the other layer.

13. The non-transitory computer readable medium of claim 12, wherein the data link layer data identifies the number of credits available at the receiver.

14. A system-on-a-chip (SoC) embedded within a mobile device, comprising:

a protocol stack including layers to communicate data over a point to point interconnect, wherein the protocol stack including layers comprises a physical layer, a data link layer, and at least one layer higher than the physical layer and data link layer to generate packets corresponding to transactions over the interconnect;

a first device to receive data link layer data from a second device indicating a number of credits allocated to a transmitter of the first device by the second device, wherein the first device has a first register and a second register associated with the transmitter, the transmitter is to transmit data on the interconnect, the first register is to store a number of credits allocated to the transmitter by the second device, and the second register is to store a total number of the allocated credits used by the transmitter; and

the second device comprising a receiver having at least one register, wherein the at least one register of the receiver is to store a total number of credits allocated to the transmitter by the receiver,

wherein the data link layer provides flow control based on the credits and provides error detection based on error correction codes added to packets generated in the other layer.

15. The SoC of claim 14 is an embedded component within a cellular phone.