High capacity memory system

• US 9,837,132 B2
• Filed: 09/24/2014
• Issued: 12/05/2017
• Est. Priority Date: 09/24/2013
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Rajan, Suresh
• Primary Examiner(s): HUANG, MIN
• Application Number:
  US15/024,454
• Publication Number:
  US 20160217839A1
• Time in Patent Office: 1,168 Days
• Field of Search: 710104
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

The embodiments described herein describe technologies for memory systems. One implementation of a memory module includes multiple device sites coupled to the a data query (DQ) buffer component via data lines and coupled to a command and address (CA) buffer component via chip select (CS) lines. A first number of the CS lines between the CA buffer component and any combination of two or more of the multiple device sites is greater than a second number of the CS lines between the CA buffer component and a single one of the multiple device sites.

Claims

1. A memory module comprising:

a circuit board;

a data buffer component disposed on the circuit board;

a command and address (CA) buffer component disposed on the circuit board; and

a plurality of device sites on the circuit board, wherein the plurality of device sites is coupled to the data buffer component via data lines and coupled to the CA buffer component via a second number of secondary chip select (CS) lines, wherein a third number of the secondary CS lines between the CA buffer component and any combination of two or more device sites of the plurality of device sites is greater than a fourth number of the secondary CS lines between the CA buffer component and a single one device site of the plurality of device sites, wherein each device site of the plurality of device sites comprises a plurality of stacked memory components, wherein each memory component of the plurality of stacked memory components at each of the plurality of device sites connects to a different one of the secondary CS lines, wherein the second number of secondary CS lines equals one-third of a total number of memory components of the plurality of stacked memory components at each of the plurality of device sites of the memory module.

2. The memory module of claim 1, wherein each of the secondary CS lines corresponds to a different rank of the memory module.

3. The memory module of claim 1, wherein each device site of the plurality of device sites comprises at least one of a package stack of the plurality of stacked memory components or a die stack of the plurality of stacked memory components.

14. The memory module of claim 1, further comprising a first number of primary chip select (CS) lines coupled between the CA buffer component and respective ones of a plurality of pins of the circuit board, wherein the first number of primary CS lines is less than a fifth number of ranks of the memory module.

4. An apparatus comprising

a motherboard substrate with at least three memory module sockets, wherein at least one of the at least three memory module sockets is populated with a memory module comprising a plurality of device sites, a data buffer component, and a command and address (CA) buffer component, wherein the plurality of device sites is coupled to the data buffer component via data lines and coupled to the CA buffer component via a total number of secondary chip select (CS) lines, wherein a first number of the secondary CS lines between the CA buffer component and any combination of two or more device sites of the plurality of device sites is greater than a second number of the secondary CS lines between the CA buffer component and a single one device site of the plurality of device sites, wherein each device site of the plurality of device sites comprises a plurality of stacked memory components, wherein each memory component of the plurality of stacked memory component at each of the plurality of device sites connects to a different one of the secondary CS lines, wherein the total number of secondary CS lines equals one-third of a total number of memory components of the plurality of stacked memory components at each of the plurality of device sites of the memory module.

5. The apparatus of claim 4, wherein each of the secondary CS lines corresponds to a different rank of the memory module.

6. The apparatus of claim 4, wherein each device site of the plurality of device sites comprises at least one of a package stack of the plurality of stacked memory components or a die stack of the plurality of stacked memory components.

7. The apparatus of claim 4, wherein the at least three memory module sockets comprises a total of six memory module sockets.

8. The apparatus of claim 4, wherein the at least three memory module sockets comprises a total of three memory module sockets.

9. The apparatus of claim 4, wherein the plurality of device sites is part of a six-device memory site.

15. The apparatus of claim 4, wherein the motherboard substrate comprises a third number of primary chip select (CS) lines coupled to CA buffer component of the memory module, wherein the third number of primary CS lines is less than a fourth number of ranks of the memory module.

10. An apparatus comprising

a motherboard substrate with at least three memory module sockets, wherein at least one of the at least three memory module sockets is populated with a memory module comprising a plurality of device sites, a data buffer component, and a command and address (CA) buffer component, wherein the plurality of device sites is coupled to the data buffer component via data lines and coupled to the CA buffer component via chip select (CS) lines, wherein a first number of the CS lines between the CA buffer component and any combination of two or more device sites of the plurality of device sites is greater than a second number of the CS lines between the CA buffer component and a single one device site of the plurality of device sites, wherein the plurality of device sites is part of a six-device memory site, wherein the memory module comprises two additional six-device memory sites, each of the two additional six-device memory sites being coupled to an additional data buffer component and coupled to the CA buffer component.

11. A memory module comprising:

a plurality of module connector pins;

a plurality of memory components;

a command and address (CA) buffer component;

a data buffer component;

a first number of data lines coupled between respective ones of the plurality of module connector pins and the data buffer component;

a second number of data lines coupled between the data buffer component and the plurality of memory components;

a third number of primary chip select (CS) lines coupled between respective ones of the plurality of module connector pins and the CA buffer component; and

a fourth number of secondary CS lines coupled between the CA buffer component and the plurality of memory components, wherein the third number of primary CS lines is less than a fifth number of ranks of the memory module, wherein the fourth number of secondary CS lines equals one-third of a total number of memory dies of the plurality of memory components.

12. The memory module of claim 11, wherein each of the plurality of memory components is at least one of a single memory device, a package stack of at least two memory devices, or a die stack of at least two memory devices.

13. The memory module of claim 11, wherein the fourth number of secondary CS lines equals a total number of memory dies of the plurality of memory components coupled to the data buffer component.