Multi-level flash storage device with minimal read latency

• US 9,837,145 B2
• Filed: 08/28/2015
• Issued: 12/05/2017
• Est. Priority Date: 08/28/2015
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Wilson, Bruce Alexander
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): Begum, Sultana
• Application Number:
  US14/839,535
• Publication Number:
  US 20170062045A1
• Time in Patent Office: 830 Days
• Field of Search: None
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A memory system, non-volatile solid-state memory, and a method of efficiently reading data from a flash memory array are disclosed. The disclosed memory system includes a flash memory array having a plurality of memory cells that store data therein, each of the plurality of memory cells being configured to store at least two bits per cell and being organized into pages, and a controller configured to read any bit of data from a page of the flash memory array by applying a single threshold voltage to the flash memory array. Reading data from the flash memory array with a single threshold greatly decreases the latency associated with the read operation.

Claims

1. A memory system, comprising:

a flash memory array having a plurality of memory cells that store data therein, each of the plurality of memory cells being organized into pages on different media of the flash memory array; and

a controller configured to read a page of a selected one of the different media by applying a single threshold voltage to the flash memory array,

wherein a combination of at least two of the plurality of memory cells is assigned to one of multiple possible states to store the data,

wherein the controller reads the page of the selected one of the different media with the single threshold voltage that corresponds to one of multiple possible threshold voltages associated with the multiple possible states, and

wherein the controller selects the single threshold voltage from a table that contains a mapping of the multiple threshold voltages to the pages of the different media such that the single threshold voltage for reading the page varies based on which of the different media is the selected one of the different media.

2. The memory system of claim 1, wherein each of the multiple possible threshold voltages are represented in the table by at least two bits, wherein the plurality of memory cells comprise Multi-Level Cells (MLCs), wherein the data is multi-bit data, and wherein the flash memory array is organized into at least three pages.

3. The memory system of claim 2, wherein each of the at least three pages has its own threshold voltage that is used to read data therefrom.

4. The memory system of claim 2, wherein the combination of the at least two of the plurality of memory cells is a first MLC cell and a second MLC cell that collectively store no more than three bits.

5. The memory system of claim 4, wherein the multiple possible states are eight possible states, wherein the multiple possible threshold voltages are three possible threshold voltages, and wherein the controller is configured to read the no more than three bits stored in the first MLC cell and the second MLC cell with the single threshold voltage that corresponds to one of the three possible threshold voltages.

6. The memory system of claim 1, wherein the plurality of memory cells comprise Triple-Level Cells (TLCs) such that the combination of the at least two of the plurality of memory cells is a combination of at least four of the plurality of memory cells, and wherein the flash memory array is organized into at least seven pages.

7. The memory system of claim 6, wherein each of the at least seven pages has its own threshold voltage that is used to read data therefrom.

8. The memory system of claim 6, wherein the combination of the at least four of the plurality of memory cells is a first TLC cell, a second TLC cell, a third TLC cell, and a fourth TLC cell that collectively store no more than eight bits.

9. The memory system of claim 8, wherein the multiple possible states are twelve possible states, wherein the multiple possible threshold voltages are seven possible threshold voltages, and wherein the controller is configured to read the no more than eight bits stored in the first TLC cell, the second TLC cell, the third TLC cell, and the fourth TLC cell with the single threshold voltage that corresponds to one of the seven possible threshold voltages.

10. The memory system of claim 1, wherein the flash memory array comprises a NAND flash memory array.

11. A non-volatile solid-state memory, comprising:

a plurality of memory cells that store data therein, each of the plurality of memory cells being organized into pages on different media of the non-volatile solid-state memory,

wherein each page of a selected one of the different media is readable with a single threshold value,

wherein a combination of at least two of the plurality of memory cells is assigned to one of multiple possible states to store the data,

wherein each page is readable with the single threshold value that corresponds to one of multiple possible threshold values associated with the multiple possible states,

wherein the multiple possible threshold values are mapped to the pages of the different media in a table such that the single threshold value for reading each page varies based on which of the different media is the selected one of the different media, and

wherein each of the multiple possible threshold values are represented in the table by at least two bits.

12. The memory of claim 11, wherein the plurality of memory cells comprise Multi-Level Cells (MLCs), and wherein the data is multi-bit data.

13. The memory of claim 12, wherein the plurality of memory cells are organized into at least three pages, each of which has its own threshold value that is used to read data therefrom.

14. The memory of claim 13, wherein the combination of the at least two of the plurality of memory cells is a first MLC cell and a second MLC cell that collectively store no more than three bits.

15. The memory of claim 14, wherein the multiple possible states are eight possible states, wherein the multiple possible threshold values are three possible threshold values, and wherein the three bits stored in the combination of the first MLC cell and the second MLC cell are readable with the single threshold value that corresponds to one of the three possible threshold values.

16. The memory of claim 11, wherein the plurality of memory cells comprise Triple-Level Cells (TLCs) such that the combination of the at least two of the plurality of memory cells is a combination of at least four of the plurality of memory cells.

17. The memory of claim 16, wherein the plurality of memory cells are organized into at least seven pages, each of which has its own threshold value that is used to read data therefrom.

18. The memory of claim 17, wherein the combination of the at least four of the plurality of memory cells is a first TLC cell, a second TLC cell, a third TLC cell, and a fourth TLC cell in the plurality of memory cells collectively store no more than eight bits.

19. The memory of claim 18, wherein the multiple possible states are twelve possible states, wherein the multiple possible threshold values are seven possible threshold values, and wherein the eight bits stored in the first TLC cell, the second TLC cell, the third TLC cell, and the fourth TLC cell are readable with the single threshold value that corresponds to one of the seven possible threshold values.

20. A method, comprising:

receiving a request to read data from a page of a selected one of different media of a flash memory array, the flash memory array including a plurality of memory cells;

determining a single voltage threshold to apply in connection with the request;

applying the single voltage threshold to a word line of the selected one of the different media in the flash memory array; and

reading an entirety of the page using the single applied voltage threshold,

wherein a combination of at least two of the plurality of memory cells is assigned to one of multiple possible states to store the data,

wherein the reading includes reading the page with the single voltage threshold that corresponds to one of multiple possible voltage thresholds associated with the multiple possible states, and

wherein the determining the single voltage threshold includes selecting the single voltage threshold from a table that contains a mapping of the multiple possible voltage thresholds to the pages of the different media such that the single voltage threshold for reading the page varies based on which of the different media is the selected one of the different media.