Storage device and operating method of storage device

• US 9,837,156 B2
• Filed: 03/06/2015
• Issued: 12/05/2017
• Est. Priority Date: 07/08/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Seol, Changkyu, Kong, Junjin, Kim, JongHa, So, Hyejeong, Son, Hong Rak, Choi, Seonghyeog
• Primary Examiner(s): Rossiter, Sean D
• Assistant Examiner(s): Doan, Khoa D
• Application Number:
  US14/640,653
• Publication Number:
  US 20160011807A1
• Time in Patent Office: 1,005 Days
• Field of Search: None
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

The operating method of the storage device includes receiving write data to be written at the plurality of memory cells; determining whether the received write data is LSB data to be written at the plurality of memory cells; and encoding the write data according to the determination. The write data is encoded according to the write data when the write data is LSB data to be written at the plurality of memory cells. The write data is encoded according to the write data and encoding data of lower data of the write data to be written at the plurality of memory cells when the write data is not LSB data to be written at the plurality of memory cells.

Claims

1. An operating method of a storage device which includes a nonvolatile memory including a plurality of memory cells;

and a memory controller adapted to control the nonvolatile memory, the operating method comprising;

receiving write data to be written at the plurality of memory cells, the write data including least significant bit (LSB) data, central significant bit (CSB) data, and most significant bit (MSB) data;

before writing the write data to the plurality of memory cells, encoding the write data by,

encoding the LSB data by changing values of the LSB data,

encoding the CSB data by changing values of the CSB data based on lower data of the CSB data, and

encoding the MSB data by changing values of the MSB data based on lower data of the MSB data,

the lower data of the CSB data being the LSB data,

the lower data of the MSB data being the CSB data and the LSB data.

2. The operating method of claim 1, wherein an LSB, a CSB and an MSB are written at each of the plurality of memory cells,

wherein data that is written as LSBs of data to be written at the plurality of memory cells and is first received is the LSB data,

wherein data that is written as CSBs of data to be written at the plurality of memory cells and is received following the LSB data is the CSB data, and

wherein data that is written as MSBs of data to be written at the plurality of memory cells and is received following the CSB data is the MSB data.

3. The operating method of claim 1, further comprising:

programming each of the plurality of memory cells to have one of at least first to eighth threshold voltage states, each of the at least first to eighth threshold voltage states corresponding to a combination of an LSB, central significant bit (CSB), and most significant bit (MSB), the at least first to eighth threshold voltage states corresponding to at least first to eighth threshold voltage distribution ranges, respectively,

wherein the encoding the LSB data includes encoding the LSB data such that a number of bits in the write data corresponding to an LSB value that is the same as an LSB value of a highest threshold voltage state is reduced, the highest threshold voltage state being the threshold voltage state, from among the at least first to eighth threshold voltage states, that corresponds to a highest threshold voltage distribution range, the highest threshold voltage distribution range being a highest one of the at least first to eighth threshold voltage distribution ranges.

4. The operating method of claim 3, wherein the encoding the CSB data comprises:

detecting bits, from among the encoded LSB data, having a same value as the LSB value of the highest threshold voltage state; and

encoding the CSB data such that, with respect to first data, a number of bits in the first data corresponding to a CSB value that is the same as a CSB value of the highest threshold voltage state, is reduced,

the first data being data, from among the write data, for which values of the encoded LSB data are the same as the LSB value of the highest threshold voltage state.

5. The operating method of claim 4, wherein the encoding the MSB data comprises:

detecting bits, from among the encoded LSB data, having a same value as the LSB value of the highest threshold voltage state;

detecting bits, from among the encoded CSB data, having a same value as the CSB value of the highest threshold voltage state; and

encoding the MSB data such that, with respect to second data, a number of bits in the second data corresponding to a MSB value that is the same as a MSB value of the highest threshold voltage state, is reduced,

the second data being data, from among the write data, for which values of the encoded LSB data are the same as the LSB value of the highest threshold voltage state and values of the encoded CSB data are the same as the CSB value of the highest threshold voltage state.

6. The operating method of claim 1, wherein the encoding the write data includes encoding the write data such that the write data is encoded according to encoding data of second data to be written at second memory cells adjacent to the plurality of memory cells.

7. The operating method of claim 6, further comprising:

writing the encoded write data such that at least an LSB, a CSB, and an MSB are written at each of the plurality of memory cells and each of the second memory cells,

wherein each of the plurality of memory cells and each of the second memory cells has one of the at least first to at least eight threshold voltage states, the at least first to at least eighth threshold voltage states each corresponding to values for an LSB, a CSB, and an MSB, the at least first to eighth threshold voltage states corresponding to at least first to eighth threshold voltage distribution ranges, respectively,

wherein locations of bits, corresponding to a highest threshold voltage state, from among at least first through eighth threshold voltage states, are detected from the encoding data of the second data, and

wherein the write data is encoded such that data corresponding to a lowest threshold voltage state, from among the at least first through eighth threshold voltage states, are not written in memory cells at the detected locations,

the highest threshold voltage state being the threshold voltage state, from among the at least first to eighth threshold voltage states, that corresponds to a highest threshold voltage distribution range, the highest threshold voltage distribution range being a highest one of the at least first to eighth threshold voltage distribution ranges,

the lowest threshold voltage state being the threshold voltage state, from among the at least first to eighth threshold voltage states, that corresponds to a lowest threshold voltage distribution range, the lowest threshold voltage distribution range being a lowest one of the at least first to eighth threshold voltage distribution ranges.

8. The operating method of claim 1, further comprising:

dividing the write data into first write data, second write data, and third write data,

wherein the first write data is selected as the LSB data to be written at the plurality of memory cells as first bits, the second write data is selected as the CSB data to be written at the plurality of memory cells as second bits, and the third write data is selected as the MSB data to be written at the plurality of memory cells as third bits.

9. The operating method of claim 8, wherein the nonvolatile memory further comprises:

first latches, second latches, and third latches connected to the plurality of memory cells, respectively;

second memory cells connected to a same word line as the plurality of memory cells; and

fourth latches, fifth latches, and sixth latches connected to the second memory cells, respectively,

wherein the operating method further includes,

loading encoding data of the first write data on the first latches;

loading encoding data of the second write data on the second latches; and

loading encoding data of the third write data on the third latches.

10. The operating method of claim 9, further comprising:

respectively loading next encoding data on the fourth latches, the fifth latches, and the sixth latches, and then, writing the data loaded on the first to sixth latches at the plurality of memory cells and the second memory cells.

11. An operating method of a storage device which includes a nonvolatile memory including a plurality of memory cells;

and a memory controller adapted to control the nonvolatile memory, the operating method comprising;

receiving write data to be written, as a plurality of data units, to the plurality of memory cells,

each of the plurality of data units corresponding to one of at least first through eighth threshold voltage states,

each of the at least first through eighth threshold voltage states corresponding to a different one of a plurality of multi-bit data values,

each of the multi-bit data values including a least significant bit (LSB), at least one central significant bit (CSB), and a most significant bit (MSB);

dividing the write data based on significance of bits of the write data; and

before writing the write data to the plurality of memory cells, encoding the write data by,

changing values of LSB data, from among the write data,

changing values of CSB data, from among the write data, based on data, from among the LSB data, that corresponds to the CSB data, and

changing values of MSB data, from among the write data, based on data, from among the LSB data and CSB data, that corresponds to the MSB data.

12. The method of claim 11, wherein the encoding includes encoding the write data such that a number of data units, from among the plurality of data units, having a same multi-bit data value as a highest multi-bit data value is reduced,

the at least first to eighth threshold voltage states corresponding to at least first to eighth threshold voltage distribution ranges, respectively,

the highest multi-bit data value being the multi-bit data value, from among the plurality of multi-bit data values, to which a highest threshold voltage state corresponds,

the highest threshold voltage state being the threshold voltage state, from among the at least first to eighth threshold voltage states, that corresponds to a highest threshold voltage distribution range,

the highest threshold voltage distribution range being a highest one of the at least first to eighth threshold voltage distribution ranges.

13. The method of claim 11, wherein the CSB data includes a first plurality of CSBs and a second plurality of CSBs, and the encoding includes encoding the CSB data such that,

values of the first plurality of CSBs are changed based on,

a combination of the first CSBs and bits of encoding data of the LSB data corresponding to the first CSBs, and

values of the second plurality of CSBs are changed based on the second plurality of CSBs regardless of the encoding data of the LSB data.

14. The method of claim 11, wherein the MSB data includes a first plurality of MSBs and a second plurality of MSBs, and the encoding includes encoding the MSB data such that,

values of the first plurality of MSBs are changed based on,

a combination of the first MSBs, bits of encoding data of the CSB data corresponding to the first MSBs, and bits of encoding data of the LSB data corresponding to the first MSBs, and

values of the second plurality of MSBs are changed based on the second plurality of MSBs regardless of the encoding data of the LSB data and regardless of the encoding data of the CSB data.

15. The method of claim 11, wherein the nonvolatile memory comprises a three-dimensional memory array which includes the plurality of memory cells.

16. The method of claim 15, wherein the three-dimensional memory array is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.

17. The method of claim 15, wherein each of the memory cells includes a charge trap later.

18. The method of claim 15, wherein word lines and/or bit lines in the three-dimensional array are shared between levels.

19. The method of claim 11, wherein the nonvolatile memory includes a plurality of strings arranged in rows and columns on a substrate,

wherein each string includes at least one select transistor and memory cells stacked on a direction perpendicular to the substrate.