Methods for manufacturing semiconductor devices

• US 9,837,280 B2
• Filed: 08/05/2016
• Issued: 12/05/2017
• Est. Priority Date: 11/21/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Dresden GmbH & Co. KG (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Dresden GmbH (Infineon Technologies AG)
• Inventors: Sorschag, Kurt, Sarlette, Daniel, Braun, Felix, Heller, Marcel, Kaiser, Dieter, Meusel, Ingo, Lemke, Marko, Mauder, Anton, Strack, Helmut
• Primary Examiner(s): Maruf, Sheikh
• Application Number:
  US15/229,632
• Publication Number:
  US 20160343577A1
• Time in Patent Office: 487 Days
• Field of Search: 438285, 438259, 438270, 438429, 438580, 438504, 438700, 257494, 257471, 257336, 257331, 257E21214, 257E21305
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02658 Pretreatments cleaning in general H01L21/02041
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/311 Etching the insulating layers by chemical or physical means H01L21/31058 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A method for forming a semiconductor device includes providing a semiconductor substrate having an upper side and comprising, in a vertical cross-section substantially orthogonal to the upper side, a plurality of semiconductor mesas of a first monocrystalline semiconductor material which are spaced apart from each other by sacrificial layers selectively etchable with respect to the first monocrystalline semiconductor material and arranged in trenches extending from the upper side into the semiconductor substrate, forming on the semiconductor mesas a support structure mechanically connecting the semiconductor mesas, at least partly replacing the sacrificial layers while the semiconductor mesas remain mechanically connected via the support structure, and at least partly removing the support structure.

Claims

1. A method for forming a semiconductor device, the method comprising:

providing a semiconductor substrate having an upper side and comprising, in a vertical cross-section substantially orthogonal to the upper side, a plurality of semiconductor mesas of a first monocrystalline semiconductor material which are spaced apart from each other by sacrificial layers selectively etchable with respect to the first monocrystalline semiconductor material and arranged in trenches extending from the upper side into the semiconductor substrate;

forming on the semiconductor mesas a support structure mechanically connecting the semiconductor mesas;

at least partly replacing the sacrificial layers while the semiconductor mesas remain mechanically connected via the support structure; and

at least partly removing the support structure.

2. The method of claim 1, wherein at least partly replacing the sacrificial layers comprises at least one of etching the sacrificial layers selective to the semiconductor mesas to expose sidewalls of the semiconductor mesas, and thermal oxidizing the sidewalls;

and/or wherein the support structure is formed substantially above the semiconductor mesas.

3. The method of claim 1, wherein the sacrificial layers comprise a dielectric material, carbon, diamond-like carbon, a photo resist, a polycrystalline semiconductor material, an amorphous semiconductor material and/or a second monocrystalline semiconductor material different to the first monocrystalline semiconductor material.

4. A method for forming a semiconductor device, the method comprising:

providing a semiconductor substrate comprising an upper side and a semiconductor layer comprised of a semiconductor material and extending to the upper side;

etching wide trenches from the upper side into the semiconductor layer so that first semiconductor mesas are formed which are separated from each other by the wide trenches and connected by semiconductor portions comprised of the semiconductor material;

forming dielectric layers at least at sidewalls of the first semiconductor mesas; and

performing a selective epitaxial growth process to fill at least one of the wide trenches with a second semiconductor mesa.

5. The method of claim 4, wherein forming the dielectric layers comprises oxidizing the sidewalls of the first semiconductor mesas and/or at least partially oxidizing the semiconductor portions.

6. The method of claim 4, wherein the dielectric layers are formed such that they are substantially ring-shaped when viewed from above.