Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units

• US 9,837,303 B2
• Filed: 06/14/2013
• Issued: 12/05/2017
• Est. Priority Date: 03/23/2012
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Inventors: Lin, Yaojian, Chen, Kang, Gu, Yu, Marimuthu, Pandi Chelvam
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US13/917,982
• Publication Number:
  US 20130277851A1
• Time in Patent Office: 1,635 Days
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24155 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor die;

disposing a modular interconnect unit including a plurality of interconnect structures adjacent to the semiconductor die;

depositing an encapsulant over the semiconductor die and modular interconnect unit;

removing a first portion of the encapsulant extending to a surface of the semiconductor die while leaving a second portion of the encapsulant over the modular interconnect unit;

forming a first insulating layer over the semiconductor die and modular interconnect unit;

forming a plurality of openings in the first insulating layer over a first interconnect structure of the plurality of interconnect structures with each opening of the plurality of openings extending to a surface of the first interconnect structure leaving a continuous portion of the first insulating layer between the plurality of openings over the surface of the first interconnect structure; and

forming a conductive layer over the first insulating layer and into the plurality of openings to contact the first interconnect structure.

2. The method of claim 1, wherein the openings include a ring shape, cross shape, or lattice shape.

3. The method of claim 1, further including forming a second insulating layer over the conductive layer, wherein the second insulating layer includes a thickness of less than 25 micrometers.

4. The method of claim 1, further including planarizing a surface of the conductive layer.

5. The method of claim 1, wherein a first opening of the plurality of openings includes a width of 20 to 30 micrometers.

6. A method of making a semiconductor device, comprising:

providing a semiconductor die;

disposing an interconnect unit including a conductive via in a peripheral region of the semiconductor die;

forming a first insulating layer over the semiconductor die and conductive via;

forming a first opening in the first insulating layer over the conductive via;

forming a second opening in the first insulating layer over the conductive via, wherein the first opening and second opening each include a width less than a width of the conductive via leaving a continuous portion of the first insulating layer around the first opening and second opening over the conductive via; and

forming a conductive layer over the first insulating layer and in the first opening and second opening of the first insulating layer over the conductive via.

7. The method of claim 6, further including forming a second insulating layer over the conductive layer, wherein the second insulating layer includes a thickness of less than 25 micrometers.

8. The method of claim 6, wherein the first opening includes a circular shape, ring shape, cross shape, or lattice shape.

9. The method of claim 6, wherein the width of the first opening is 20 to 30 micrometers.

10. The method of claim 6, wherein a pitch of the first opening and second opening is 40 micrometers.

11. The method of claim 6, further including:

forming an encapsulant over the semiconductor die and conductive via; and

removing a portion of the encapsulant over the conductive via.

12. The method of claim 6, further including:

forming an encapsulant over the semiconductor die and interconnect unit; and

removing a first portion of the encapsulant extending to a surface of the semiconductor die while leaving a second portion of the encapsulant over the interconnect unit.

13. A semiconductor device, comprising:

a semiconductor die;

an interconnect unit disposed in a peripheral region of the semiconductor die including an array of interconnect structures;

a first insulating layer formed over the interconnect unit, wherein the first insulating layer includes a plurality of individual openings formed over a first interconnect structure in the array of interconnect structures and extending to a surface of the first interconnect structure while leaving a portion of the first insulating layer between the plurality of individual openings over the surface of the first interconnect structure; and

a conductive layer formed over the first insulating layer and into the plurality of individual openings over the first interconnect structure.

14. The semiconductor device of claim 13, wherein a pitch of the individual openings is 40 micrometers.

15. The semiconductor device of claim 13, wherein the individual openings include a circular shape, ring shape, cross shape, or lattice shape.

16. The semiconductor device of claim 13, further including a second insulating layer formed over the conductive layer and first insulating layer.

17. The semiconductor device of claim 16, wherein the second insulating layer includes a thickness of less than 25 micrometers.

18. The semiconductor device of claim 13, further including

an encapsulant formed over the semiconductor die and interconnect structure with

an opening formed in the encapsulant over the interconnect structure.

19. A semiconductor device, comprising:

a semiconductor die;

an interconnect unit disposed in a peripheral region of the semiconductor die, wherein the interconnect unit includes a conductive via formed through the interconnect unit; and

a first insulating layer formed over the semiconductor die and interconnect unit including a first opening of the first insulating layer formed over a first portion of the conductive via and a second opening of the first insulating layer formed over a second portion of the conductive via, wherein the first opening and second opening extend to a surface of the conductive via leaving a portion of the first insulating layer around the first opening and second opening over the surface of the conductive via.

20. The semiconductor device of claim 19, wherein a pitch of the first opening and second opening is 40 micrometers.

21. The semiconductor device of claim 19, wherein the first opening and second opening include a circular shape, ring shape, cross shape, or lattice shape.

22. The semiconductor device of claim 19, further including:

a conductive layer formed over the first insulating layer and into the first opening and second opening over the conductive via; and

a second insulating layer formed over the conductive layer and first insulating layer.

23. The semiconductor device of claim 22, wherein a surface of the conductive layer is planar.