Semiconductor via structure with lower electrical resistance

• US 9,837,309 B2
• Filed: 11/19/2015
• Issued: 12/05/2017
• Est. Priority Date: 11/19/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Clevenger, Lawrence A., Li, Baozhen, Peterson, Kirk D., Spooner, Terry A., Wang, Junli
• Primary Examiner(s): Coleman, William
• Assistant Examiner(s): LY, KIEN C
• Application Number:
  US14/945,640
• Publication Number:
  US 20170148673A1
• Time in Patent Office: 747 Days
• Field of Search: None
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53209 based on metals, e.g. alloys, metal silicides H01L23/53285 takes precedence
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers

Abstract

A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.

Claims

1. A method for forming a semiconductor device, the method comprising:

forming a first liner material in a first insulator layer;

depositing a first conductive material in the first insulator layer to form a first conductive line;

depositing an insulator material on the first conductive line;

forming a via in the insulator material;

removing a portion of the insulator material from the via to expose a portion of the first conductive line;

depositing a second liner material in the via and over the exposed portion of the first conductive line;

removing a portion of the second liner material to expose a portion of the first conductive line;

depositing a via material on the exposed portion of the first conductive line and in the via, wherein the via material is in contact with the first conductive material;

depositing a third liner material over the via material and the second liner material in the via; and

depositing a second conductive material in the third liner material.

2. The method of claim 1, wherein the first liner material and the second liner material may be independently selected from the group consisting of titanium, titanium nitride, tungsten, titanium tungsten, tungsten nitride, tantalum, TaN, TaN/Ta, Ta/TaN, Ta/TaN/Ta, or combinations thereof.

3. The method of claim 1, wherein the via material includes a conductive material.