Systems and methods for creating fluidic assembly structures on a substrate

• US 9,837,390 B1
• Filed: 11/07/2016
• Issued: 12/05/2017
• Est. Priority Date: 11/07/2016
• Status: Active Grant

• Current Assignee: Corning Incorporated
• Original Assignee: Corning Incorporated
• Inventors: Sorensen, Michael Lesley, Garner, Sean Mathew
• Primary Examiner(s): Kusumakar, Karen
• Application Number:
  US15/344,736
• Time in Patent Office: 393 Days
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/8014 Guiding structures outside the body
• CPC Class Codes: H01L 2224/80904 by means of an encapsulation layer or foil
• CPC Class Codes: H01L 2224/95085 being a liquid, e.g. for fluidic self-assembly
• CPC Class Codes: H01L 2224/95101 in a liquid medium
• CPC Class Codes: H01L 2224/95136 involving guiding structures, e.g. shape matching, spacers or supporting members
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/08 of an individual bonding area
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/95 at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 24/98 Methods for disconnecting semiconductor or solid-state bodies
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15151 the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 1/186 manufactured by mounting on or connecting to patterned circuits before or during embedding
• CPC Class Codes: H05K 2201/09072 : Hole or recess under component or special relationship between hole and component
• CPC Class Codes: H05K 2201/10106 : Light emitting diode [LED]
• CPC Class Codes: H05K 2201/10128 : Display
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2203/1316 : Moulded encapsulation of mounted components
• CPC Class Codes: H05K 2203/1327 : Moulding over PCB locally or completely applying non-metallic protective coatings for encapsulating mounted components H05K3/284
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence
• CPC Class Codes: H05K 3/285 : Permanent coating compositions

Abstract

Embodiments are related to fluidic assembly and, more particularly, to systems and methods for forming physical structures on a substrate.

Claims

1. An assembly panel, the panel comprising:

a substrate having a top surface;

an electronics structure layer disposed over the top layer of the substrate;

a sol-gel based structural layer disposed over the top layer of the substrate and the electronics structure layer, wherein the sol-gel based structural layer includes openings exposing at least a part of the electronics structure layer; and

wherein the sol-gel based structural layer is formed of a material including at least two materials selected from a group consisting of;

hydroxy(polydimethylsiloxane), methyltriethoxysilane, phenyltriethoxysilane, tetraethylorthosilicate, water, and octyltrichlorosilane.

2. The assembly panel of claim 1, wherein the electronics structure layer exhibits a first thickness and the sol-gel based structural layer exhibits a second thickness, and wherein the second thickness is at least three times thicker than the first thickness.

3. The assembly panel of claim 2, wherein the second thickness is at least five times thicker than the first thickness.

4. The assembly panel of claim 1, wherein the electronics structure layer includes an electrically conductive material connecting a bottom area of a first of the openings to a bottom area of a second of the openings.

5. The assembly panel of claim 1, wherein a material of the substrate is selected from a group consisting of:

polymer, metal, ceramic, glass, and glass-ceramic.

6. The assembly panel of claim 1, wherein vias extend through the substrate from the bottom of a subset of the openings.

7. The assembly panel of claim 1, wherein the substrate is a multi-layer substrate.

8. A method for manufacturing a device, the method comprising:

providing a substrate; and

forming a sol-gel based structural layer over the substrate using a solution-based process, wherein the sol-gel structural layer includes features having varying feature depths.

9. The method of claim 8, wherein the solution-based process is a subtractive process.

10. The method of claim 8, wherein the varying feature depth includes openings in the sol-gel based structural layer through which an underlying layer is exposed.

11. The method of claim 10, wherein the method further comprises:

forming an electronics structure layer over the substrate prior to forming the sol-gel based structural layer over the substrate such that the sol-gel based structural layer covers at least a portion of the electronics structure layer; and

wherein the underlying layer is selected from a group consisting of;

the electronics structure layer, and the top surface of the substrate.

12. The method of claim 11, the method further comprising:

using fluidic assembly to deposit micro-devices in the openings; and

forming an encapsulation layer over the sol-gel based structural layer and the micro-devices.

13. The method of claim 12, wherein the micro-devices are light emitting diodes.

14. The method of claim 12, wherein forming the encapsulation layer includes depositing a sol-gel material over the substrate, and curing the sol-gel material.

15. The method of claim 8, wherein the solution-based process is an additive process, and wherein the additive process is selected from a group of:

a replication process, a stamping process, and a printing process.

16. The method of claim 8, wherein the solution-based process is an additive process, and wherein the additive process is a printing process, and wherein the printing process is selected from a group consisting of:

screen printing, flexo printing, gravure printing, inkjet printing, and offset printing.

17. The method of claim 8, wherein the solution-based process is an additive process, and wherein the additive process includes curing a sol-gel material added over the substrate.

18. The method of claim 17, wherein curing the sol-gel material added over the substrate includes a process selected from a group consisting of:

exposing the sol-gel material to ultraviolet radiation, and exposing the sol-gel material to thermal radiation.

19. The method of claim 8, wherein the method further comprises:

forming an electronics structure layer over the substrate prior to forming the sol-gel based structural layer over the substrate such that the sol-gel based structural layer covers at least a portion of the electronics structure layer.

20. The method of claim 8, wherein vias extend through the substrate from the bottom of a subset of the openings.

21. An electronic display device, the display device comprising:

a substrate;

an electronics structure layer formed over the substrate and including a first electrically conductive trace;

a sol-gel based structural layer formed over the substrate such that the sol-gel based structural layer covers a first portion of the electronics structure layer, wherein the sol-gel structural layer includes openings though which a second portion of the electronics structure layer is exposed, and wherein the first electrically conductive trace electrically connects the bottom of at least two of the openings;

light emitting diodes each within a respective one of the openings, wherein the light emitting diodes each include an upper electrical contact and a lower electrical contact, and wherein the lower electrical contact of a subset of the light emitting diodes is electrically connected to the first electrically conductive trace;

an encapsulation layer covering at least a portion of the sol-gel based structural layer and micro-devices; and

a second electrically conductive trace electrically connecting the upper electrical contacts of two or more of the light emitting diodes.

22. The electronic display device of claim 21, wherein the electronics structure layer exhibits a first thickness and the sol-gel based structural layer exhibits a second thickness, and wherein the second thickness is at least three times thicker than the first thickness.

23. The electronic display device of claim 22, wherein the second thickness is at least five times thicker than the first thickness.

24. The electronic display device of claim 21, wherein the sol-gel based structural layer is formed of a material including at least two materials selected from a group consisting of:

a silane, a silicate, and water.

25. The electronic display device of claim 21, wherein the sol-gel based structural layer is formed of a material including at least two materials selected from a group consisting of:

hydroxy(polydimethylsiloxane), methyltriethoxysilane, phenyltriethoxysilane, tetraethylorthosilicate, water, and octyltrichlorosilane.

26. The electronic display device of claim 21, wherein a material of the substrate is selected from a group consisting of:

polymer, metal, ceramic, glass, and glass-ceramic.

27. The electronic display device of claim 21, wherein vias extend through the substrate from the bottom of a subset of the openings.

28. The electronic display device of claim 21, wherein the substrate is a multi-layer substrate.

29. An assembly panel, the panel comprising:

a substrate having a top surface;

a sol-gel based structural layer disposed adjacent to the top surface of the substrate;

an electronics structure layer disposed over the sol-gel based structural layer such that the electronics structure layer is separated from the substrate by the sol-gel structural layer; and

wherein no electronics exist between the sol-gel based structural layer and the top surface of the substrate.

30. The assembly panel of claim 29, wherein the sol-gel based structural layer is formed of a material including at least two materials selected from a group consisting of:

a silane, a silicate, and water.

31. The assembly panel of claim 29, wherein the sol-gel based structural layer is formed of a material including at least two materials selected from a group consisting of:

hydroxy(polydimethylsiloxane), methyltriethoxysilane, phenyltriethoxysilane, tetraethylorthosilicate, water, and octyltrichlorosilane.

32. The electronic display device of claim 29, wherein vias extend through the substrate from the bottom of a subset of the openings.

33. The electronic display device of claim 29, wherein the substrate is a multi-layer substrate.

34. An assembly panel, the assembly panel comprising:

a substrate; and

a solution-based structural layer disposed over the substrate having a thermal excursion capability of greater than three hundred degrees Celsius, an optical transmission of greater than eighty percent, a thickness of greater than two micrometers, and a Youngs modulus of greater than 20 GPa.

35. The assembly panel of claim 34, wherein the solution-based structural layer is made of a sol-gel material.

36. The assembly panel of claim 35, wherein the sol-gel material exhibits a feature resolution of less than ten micrometers for features having a depth of greater than fifty nanometers.

37. The assembly panel of claim 34, wherein the thermal excursion capability is greater than three hundred, fifty degrees Celsius, the optical transmission is greater than ninety percent, the thickness of greater than three micrometers, and the Youngs modulus is greater than 30 GPa.

38. An assembly panel, the panel comprising:

a substrate having a top surface;

an electronics structure layer disposed over the top layer of the substrate;

a sol-gel based structural layer disposed over the top layer of the substrate and the electronics structure layer, wherein the sol-gel based structural layer includes openings exposing at least a part of the electronics structure layer; and

wherein the sol-gel based structural layer is formed of a material including at least two materials selected from a group consisting of;

a silane, a silicate, and water.

39. The assembly panel of claim 38, wherein vias extend through the substrate from the bottom of a subset of the openings.

40. An assembly panel, the panel comprising:

a substrate having a top surface;

an electronics structure layer disposed over the top layer of the substrate;

a sol-gel based structural layer disposed over the top layer of the substrate and the electronics structure layer, wherein the sol-gel based structural layer includes openings exposing at least a part of the electronics structure layer; and

wherein vias extend through the substrate from the bottom of a subset of the openings.

41. The assembly panel of claim 40, wherein the sol-gel based structural layer is formed of a material including at least two materials selected from a group consisting of:

a silane, a silicate, and water.

42. The assembly panel of claim 40, wherein the sol-gel based structural layer is formed of a material including at least two materials selected from a group consisting of:

hydroxy(polydimethylsiloxane), methyltriethoxysilane, phenyltriethoxysilane, tetraethylorthosilicate, water, and octyltrichlorosilane.