Arrays of memory cells individually comprising a capacitor and an elevationally-extending transistor, methods of forming a tier of an array of memory cells, and methods of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor

• US 9,837,420 B1
• Filed: 01/10/2017
• Issued: 12/05/2017
• Est. Priority Date: 01/10/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ramaswamy, Durai Vishak Nirmal
• Primary Examiner(s): Tobergte, Nicholas
• Application Number:
  US15/402,463
• Time in Patent Office: 329 Days
• CPC Class Codes: C12N 15/1133 against herpetoviridae, e.g. HSV
• CPC Class Codes: C12N 2310/113 targeting other non-coding nucleic acids, e.g. antagomirs
• CPC Class Codes: C12N 2310/14 interfering N.A.
• CPC Class Codes: C12N 2310/141 MicroRNAs, miRNAs
• CPC Class Codes: C12N 2310/3231 having an additional ring, e.g. LNA, ENA
• CPC Class Codes: C12N 2710/16211 Lymphocryptovirus, e.g. human herpesvirus 4, Epstein-Barr Virus
• CPC Class Codes: C12N 2710/16263 by chemical treatment
• CPC Class Codes: C12N 7/00 Viruses; Bacteriophages; Compositions thereof; Preparation or purification thereof preparing medicinal viral antigen or antibody compositions, e.g. virus vaccines, A61K39/00
• CPC Class Codes: C12Q 1/701 Specific hybridization probes
• CPC Class Codes: C12Q 1/705 for herpetoviridae, e.g. herpes simplex, varicella zoster
• CPC Class Codes: C12Q 2600/136 Screening for pharmacological compounds
• CPC Class Codes: C12Q 2600/158 Expression markers
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/39 the capacitor and the transistor being in a same trench
• CPC Class Codes: H10B 53/30 : characterised by the memory core region

Abstract

A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells. Other methods are disclosed, as are structures independent of method of fabrication.

Claims

1. A method of forming a tier of an array of memory cells within an array area, the memory cells individually comprising a capacitor and an elevationally-extending transistor, the method comprising using two, and only two, sacrificial masking steps within the array area of the tier in forming the memory cells.

2. The method of claim 1 wherein in each of the two sacrificial masking steps exposed channel-comprising material of the transistors within the array area is subtractively etched while using sacrificial masking material above an unexposed portion of said channel-comprising material within the array area as a mask.

3. The method of claim 1 wherein in each of the two sacrificial masking steps material is subtractively etched within the array area none of which includes material of the capacitors within the array area.

4. The method of claim 1 wherein a sequentially first of the two masking steps comprises using sacrificial masking material to mask digit line material while subtractively etching exposed digit line material away to form digit lines under the sacrificial masking material and ultimately under the transistors and capacitors formed within the array area.

5. The method of claim 1 including etching gate material of the transistors to form transistor gates and all material of which the capacitors are formed is etched to form the capacitors without any masking material being there-above within the array area during such etchings.

6. The method of claim 1 comprising forming the individual memory cells to have a total of only one transistor and a total of only one capacitor.

7. The method of claim 1 comprising forming the individual memory cells to have a total of only two transistors and a total of only two capacitors.

17. The method of claim 1 wherein the tier comprises digit lines conductively interconnecting memory cells along columns of the array, at least one of the two masking steps comprising subtractively etching digit line material for forming the digit lines.

8. A method of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor, the method sequentially comprising:

using a first sacrificial mask to pattern digit line material and channel-comprising material there-above in a first direction to form digit lines within the array having lines of the channel-comprising material there-above;

using a second sacrificial mask to pattern the channel-comprising material in a second direction that is different from the first direction to cut the lines of channel-comprising material above the digit lines into spaced individual channels of individual transistors of individual memory cells within the array;

forming gate insulator and an access line laterally across and operatively laterally adjacent a lateral side of the individual transistor channels; and

forming capacitors that individually have one of their capacitor electrodes directly against a lateral side of an upper source/drain region of one of the individual transistors of the individual memory cells within the array.

18. The method of claim 8 wherein the forming of the capacitors forms individual of the one capacitor electrodes directly against a pair of two laterally-opposing sides of individual of the upper source/drain regions.

19. The method of claim 18 wherein the forming of the capacitors forms individual of the one capacitor electrodes directly against no more than two laterally-opposing sides of individual of the upper source/drain regions.

20. The method of claim 18 wherein the individual upper source/drain regions have completely encircling peripheral lateral side surfaces, the individual one capacitor electrodes being directly against all of the completely encircling peripheral lateral side surfaces of the individual upper source/drain regions.

21. The method of claim 8 comprising forming the individual memory cells to have a total of only one transistor and a total of only one capacitor.

22. The method of claim 8 comprising forming the individual memory cells to have a total of only two transistors and a total of only two capacitors.

23. The method of claim 8 wherein the one capacitor electrodes individually are formed directly against less than all of the lateral side of the respective upper source/drain region.

24. The method of claim 23 wherein the one capacitor electrodes individually are formed directly against less than half of the lateral side of the respective upper source/drain region.

9. A method of forming a tier of an array of memory cells individually comprising a capacitor and an elevationally-extending transistor, comprising:

forming digit line material over a substrate, channel-comprising material above the digit line material, and source/drain-comprising material above the channel-comprising material;

patterning the digit line material, the channel-comprising material, and the source/drain-comprising material to form digit lines within the array and to form elevationally-extending pillars comprising individual channels and individual upper source/drain regions of individual transistors of individual memory cells within the array;

forming gate insulator and an access line laterally across and operatively laterally adjacent a lateral side of the individual transistor channels;

forming a first capacitor electrode over first laterally-opposing sides of the pillars directly against a pair of first laterally-opposing sides of the individual upper source/drain regions within the array; and

forming a capacitor insulator over the first capacitor electrode and forming a second capacitor electrode over the capacitor insulator within the array.

25. The method of claim 9 wherein the patterning comprises subtractive etching using more than one sacrificial masking step within the array tier.

26. The method of claim 25 comprising forming the individual memory cells to have a total of only one transistor and a total of only one capacitor or to have a total of only two transistors and a total of only two capacitors, and using no more than two sacrificial masking steps within the array tier.

27. The method of claim 9 wherein the pillars are formed to be conductive from the upper source/drain regions to tops of the pillars.

28. The method of claim 9 wherein the pillars are formed to be non-conductive from tops of the upper source/drain regions to tops of the pillars.

29. The method of claim 28 wherein the pillars are formed to be insulative from the tops of the upper source/drain regions to the pillar tops.

30. The method of claim 28 wherein the pillars are formed to be semiconductive from the tops of the upper source/drain regions to the pillar tops.

31. The method of claim 9 wherein the access line is formed to comprise gate insulator and access line pairs extending laterally across a pair of laterally-opposing sides of the first and second pillars, the gate insulator and the access line pairs being operatively laterally adjacent laterally-opposing sides of the individual channels of individual of the first pillars within the array, the forming the gate insulator and the access line pairs comprising:

forming gate insulator over tops and the first laterally-opposing sides of the pillars and the channels and between laterally-row-adjacent of the pillars;

forming access gate material over the gate insulator, including over the pillar tops, over the first laterally-opposing sides of the pillars and the channels, and between the laterally-row-adjacent pillars; and

maskless anisotropically etching the access line material from being over the pillar tops and from being interconnected between the laterally-row-adjacent pillars and to form the access line pairs in respective individual row lines interconnecting the transistors in that row.

32. The method of claim 31 comprising conducting the maskless anisotropic etching of the access gate material in at least two time-spaced etching steps.

33. The method of claim 32 wherein a lower portion of trenches between the rows of pillars are plugged with sacrificial material during a later of the maskless anisotropic etching steps, and removing the sacrificial material prior to forming the first capacitor electrode.

34. The method of claim 9 wherein forming the first capacitor electrode comprises:

forming first capacitor electrode-comprising material over tops and the first laterally-opposing sides of the pillars directly against the first laterally-opposing sides of the individual upper source/drain regions and between laterally-row-adjacent of the pillars; and

maskless anisotropically etching the first capacitor electrode-comprising material from being over the pillar tops and from being interconnected between the laterally-row-adjacent pillars.

10. A method of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor, comprising:

forming pillars extending elevationally upward from digit lines, the pillars individually comprising an individual channel and an individual upper source/drain region of individual transistors of individual memory cells within the array;

forming gate insulator and an access line laterally across and operatively laterally adjacent a lateral side of the individual transistor channels;

forming a first capacitor electrode completely encircling and directly against all peripheral lateral sides of the individual upper source/drain regions within the array; and

forming a capacitor insulator over and completely encircling individual of the first capacitor electrodes and forming a second capacitor electrode over and completely encircling the encircling capacitor insulator within the array.

35. The method of claim 10 comprising forming the first capacitor electrode to have a top that is planar and elevationally coincident with a planar top of its encircled pillar.

36. The method of claim 10 comprising forming the first capacitor electrode to have a top that is not elevationally coincident with a top of its encircled pillar.

37. The method of claim 10 being devoid of etching material of the pillar after forming the first capacitor electrode.

38. The method of claim 10 comprising after forming the first capacitor electrode, etching material of the pillar selectively relative to the first capacitor electrode before forming the capacitor insulator.

39. The method of claim 38 comprising etching more than half of all of the pillar material away before forming the capacitor insulator.

40. The method of claim 38 comprising forming the capacitor insulator and the second capacitor electrode laterally over radially internal sides and radially external sides of a majority of individual of the first capacitor electrodes.

41. The method of claim 40 comprising forming the capacitor insulator directly against tops of the encircled individual upper source/drain regions.

42. The method of claim 40 comprising forming the capacitor insulator laterally over all of the radially external sides of the individual first capacitor electrodes and laterally over only some of the radially internal sides of the individual first capacitor electrodes.

11. A method of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor, comprising:

forming digit line material over a substrate, channel-comprising material above the digit line material, and source/drain-comprising material above the channel-comprising material;

patterning the digit line material, the channel-comprising material, and the source/drain-comprising material in a first direction to form digit lines within the array having lines of the channel-comprising material and lines of the source/drain-comprising material there-above;

forming first material in trenches that are laterally between the digit lines and the lines there-above within the array;

patterning the channel-comprising material, the source/drain-comprising material, and the first material in a second direction that is different from the first direction to form elevationally-extending pillars comprising individual channels and individual upper source/drain regions of individual transistors of individual memory cells within the array and having the first material laterally between the pillars;

forming gate insulator and access line pairs laterally across a pair of first laterally-opposing sides of the pillars operatively laterally adjacent a pair of first laterally-opposing sides of the individual channels within the array;

forming second material in trenches that are laterally between the pillars and the first material within the array;

removing the first and second materials sufficiently to expose encircling peripheral lateral sides of the individual upper source/drain regions;

forming a first capacitor electrode completely encircling and directly against all of the encircling peripheral lateral sides of the individual upper source/drain regions within the array; and

forming a capacitor insulator over and completely encircling individual of the first capacitor electrodes and forming a second capacitor electrode over and completely encircling the encircling capacitor insulator within the array.

43. The method of claim 11 wherein the first and second materials are formed to be of the same composition relative one another.

44. The method of claim 11 wherein the first and second materials are formed to be of different composition relative one another.

45. The method of claim 11 comprising forming the first capacitor electrode to have a top that is higher than a top of its encircled pillar.

12. A method of forming an array of memory cells individually comprising a capacitor and an elevationally-extending transistor, comprising:

forming alternating first and second elevationally-extending pillars, the first pillars extending elevationally upward from digit lines and individually comprising an individual channel and an individual upper source/drain region of individual transistors of individual memory cells within the array;

forming gate insulator and an access line laterally across and operatively laterally adjacent a lateral side of the individual transistor channels;

forming first capacitor electrode line pairs laterally across the first and second pillars, the first capacitor electrode line pairs being directly against a pair of first laterally-opposing sides of the individual upper source/drain regions of the individual first pillars within the array;

removing material of the second pillars from lateral sides of the first capacitor electrode line pairs and then cutting laterally through the lateral sides of the first capacitor electrode line pairs to form first capacitor electrodes that individually are directly against the first laterally-opposing sides of the individual upper source/drain regions within the array; and

providing a capacitor insulator over the first capacitor electrodes and a second capacitor electrode over the capacitor insulator within the array.

46. The method of claim 12 wherein the providing occurs after the cutting.

47. The method of claim 12 wherein the providing occurs before the cutting.

48. The method of claim 12 wherein the removing is of all material of the second pillars.

49. The method of claim 12 wherein the access line is formed to comprise gate insulator and access line pairs extending laterally across a pair of first laterally-opposing sides of the first and second pillars, the gate insulator and the access line pairs being operatively laterally adjacent first laterally-opposing sides of the individual channels of individual of the first pillars within the array.

13. An array of memory cells individually comprising a capacitor and an elevationally-extending transistor, the array comprising rows of access lines and columns of digit lines, comprising:

individual of the columns comprising a digit line under channels of elevationally-extending transistors of individual memory cells within the array and interconnecting the transistors in that column;

individual of the rows comprising an access line above the digit lines, the access line extending laterally across and operatively laterally adjacent a lateral side of the transistor channels and interconnecting the transistors in that row; and

capacitors of the individual memory cells within the array individually comprising;

a first capacitor electrode directly against a lateral side of an upper source/drain region of individual of the transistors within the array;

a capacitor insulator over the first capacitor electrode; and

a second capacitor electrode over the capacitor insulator.

50. The array of claim 13 wherein the access line comprises access line pairs extending laterally across a pair of first laterally-opposing sides of the transistor channels in that row.

51. The array of claim 13 wherein the first capacitor electrode is directly against a pair of first laterally-opposing sides of the upper source/drain region of the individual transistors within the array.

52. The array of claim 51 wherein the first capacitor electrode is directly against no more than two laterally-opposing sides of the upper source/drain region of the individual transistors within the array.

53. The array of claim 51 wherein the individual upper source/drain regions have completely encircling peripheral lateral side surfaces, the individual first capacitor electrodes being directly against all of the completely encircling peripheral lateral side surfaces of the individual upper source/drain regions.

54. The array of claim 13 wherein the first capacitor electrodes individually are directly against less than all of the lateral side of the respective upper source/drain region.

55. The array of claim 13 wherein the first capacitor electrodes individually are directly against less than half of the lateral side of the respective upper source/drain region.

56. The array of claim 13 wherein the capacitor insulator comprises programmable material.

57. The array of claim 56 wherein the capacitor insulator comprises programmable ferroelectric material.

58. The array of claim 13 wherein the individual memory cells have a total of only one transistor and a total of only one capacitor.

59. The array of claim 13 wherein the individual memory cells have a total of only two transistors and a total of only two capacitors.

14. An array of memory cells individually comprising a capacitor and an elevationally-extending transistor, the array comprising rows of access lines and columns of digit lines, comprising:

individual of the columns comprising a digit line under channels of elevationally-extending transistors of individual memory cells within the array and interconnecting the transistors in that column;

individual of the rows comprising an access line above the digit lines, the access line extending laterally across and operatively laterally adjacent a lateral side of the transistor channels and interconnecting the transistors in that row; and

capacitors of the individual memory cells within the array individually comprising;

a first capacitor electrode directly against a pair of first laterally-opposing sides of an upper source/drain region of individual of the transistors within the array;

a capacitor insulator over the first capacitor electrode; and

a second capacitor electrode over the capacitor insulator.

60. The array of claim 14 wherein the individual memory cells have a total of only one transistor and a total of only one capacitor.

61. The array of claim 14 wherein the individual memory cells have a total of only two transistors and a total of only two capacitors.

15. An array of memory cells individually comprising a capacitor and an elevationally-extending transistor, the array comprising rows of access lines and columns of digit lines, comprising:

individual of the columns comprising a digit line under channels of elevationally-extending transistors of individual memory cells within the array and interconnecting the transistors in that column;

individual of the rows comprising an access line above the digit lines, the access line extending laterally across and operatively laterally adjacent a lateral side of the transistor channels and interconnecting the transistors in that row; and

the individual memory cells comprising a pillar extending elevationally above the digit lines, the pillar comprising one of the transistor channels and an upper source/drain region of individual of the transistors, the pillar having an elevational thickness that is at least three times that of the one transistor channel; and

capacitors of the individual memory cells within the array individually comprising;

a first capacitor electrode directly against a pair of first laterally-opposing sides of the pillar and the upper source/drain region of the respective one individual transistor within the array;

a capacitor insulator over the first capacitor electrode; and

a second capacitor electrode over the capacitor insulator.

62. The array of claim 15 wherein the pillars are formed to be conductive from the upper source/drain regions to tops of the pillars.

63. The array of claim 15 wherein the pillars are formed to be non-conductive from tops of the upper source/drain regions to tops of the pillars.

64. The array of claim 63 wherein the pillars are formed to be insulative from the tops of the upper source/drain regions to the pillar tops.

65. The array of claim 63 wherein the pillars are formed to be semiconductive from the tops of the upper source/drain regions to the pillar tops.

66. The array of claim 15 wherein the first capacitor electrode has a top that is planar and elevationally coincident with a planar top of its pillar.

67. The array of claim 15 wherein the first capacitor electrode has a top that is not elevationally coincident with a top of its pillar.

68. The array of claim 67 wherein the first capacitor electrode top is planar.

69. The array of claim 15 wherein the first capacitor electrode is directly against no more than two laterally-opposing sides of the upper source/drain region of the respective one individual transistors within the array.

70. The array of claim 15 wherein the individual upper source/drain regions have completely encircling peripheral lateral side surfaces, the individual first capacitor electrodes being directly against all of the completely encircling peripheral lateral side surfaces of the individual upper source/drain regions.

16. An array of memory cells individually comprising a capacitor and an elevationally-extending transistor, the array comprising rows of access lines and columns of digit lines, comprising:

individual of the columns comprising a digit line under channels of elevationally-extending transistors of individual memory cells within the array and interconnecting the transistors in that column;

individual of the rows comprising an access line above the digit lines, the access line extending laterally across and operatively laterally adjacent a lateral side of the transistor channels and interconnecting the transistors in that row; and

capacitors of the individual memory cells within the array individually comprising;

an upwardly-open and downwardly-open first capacitor electrode cylinder completely encircling and directly against all peripheral lateral sides of an upper source/drain region of individual of the transistors within the array;

a capacitor insulator over radially outer sides and radially inner sides of the first capacitor electrode cylinder; and

a second capacitor electrode over the capacitor insulator and over the radially outer sides and the radially inner sides of the first capacitor electrode cylinder.

71. The array of claim 16 wherein the capacitor insulator and the second capacitor electrode are over a majority of the radially internal sides and a majority of the radially external sides of the first capacitor electrode cylinder.

72. The array of claim 16 wherein the capacitor insulator is laterally over all of the radially external sides of the first capacitor electrode cylinder and laterally over only some of the radially internal sides of the first capacitor electrode cylinder.

73. The array of claim 16 wherein the capacitor insulator is directly against tops of the encircled individual upper source/drain regions.

74. The array of claim 16 wherein the capacitor insulator is directly against tops of the first capacitor electrode cylinders.

75. The array of claim 16 wherein the capacitor insulator is directly against tops of the encircled individual upper source/drain regions and is directly against tops of the first capacitor electrode cylinders.