GaN transistors with polysilicon layers used for creating additional components
First Claim
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1. A method of manufacturing an integrated circuit, the method comprising:
- forming a gate structure for an enhancement mode device;
depositing a first insulating layer over the gate structure;
depositing a polysilicon layer on the first insulating layer;
doping the polysilicon layer to form at least one p-type region and at least one n-type region in the polysilicon layer;
depositing a second insulating layer on the polysilicon layer;
forming a first interconnect on the second insulating layer and electrically coupled to the n-type region of the polysilicon layer by a first via formed in the second insulating layer, and forming a second interconnect on the second insulating layer and electrically coupled to the p-type region of the polysilicon layer by a second via formed in the second insulating layer.
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Abstract
A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.
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Citations
8 Claims
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1. A method of manufacturing an integrated circuit, the method comprising:
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forming a gate structure for an enhancement mode device; depositing a first insulating layer over the gate structure; depositing a polysilicon layer on the first insulating layer; doping the polysilicon layer to form at least one p-type region and at least one n-type region in the polysilicon layer; depositing a second insulating layer on the polysilicon layer; forming a first interconnect on the second insulating layer and electrically coupled to the n-type region of the polysilicon layer by a first via formed in the second insulating layer, and forming a second interconnect on the second insulating layer and electrically coupled to the p-type region of the polysilicon layer by a second via formed in the second insulating layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification