GaN transistors with polysilicon layers used for creating additional components

• US 9,837,438 B2
• Filed: 12/04/2015
• Issued: 12/05/2017
• Est. Priority Date: 07/29/2013
• Status: Active Grant

• Current Assignee: Efficient Power Conversion Corporation
• Original Assignee: Efficient Power Conversion Corporation
• Inventors: Cao, Jianjun, Beach, Robert, Lidow, Alexander, Nakata, Alana, Zhao, Guangyuan, Ma, Yanping, Strittmatter, Robert, De Rooij, Michael A., Zhou, Chunhua, Kolluri, Seshadri, Liu, Fang-Chang, Chiang, Ming-Kun, Cao, Jiali, Jauhar, Agus
• Primary Examiner(s): Nguyen, Sophia
• Application Number:
  US14/959,710
• Publication Number:
  US 20160086980A1
• Time in Patent Office: 732 Days
• CPC Class Codes: H01L 21/7605 between components manufactured in an active substrate comprising AIII BV compounds
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42372 : characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42384 : for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/66462 : with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66765 : Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/7786 : with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

Claims

1. A method of manufacturing an integrated circuit, the method comprising:

forming a gate structure for an enhancement mode device;

depositing a first insulating layer over the gate structure;

depositing a polysilicon layer on the first insulating layer;

doping the polysilicon layer to form at least one p-type region and at least one n-type region in the polysilicon layer;

depositing a second insulating layer on the polysilicon layer;

forming a first interconnect on the second insulating layer and electrically coupled to the n-type region of the polysilicon layer by a first via formed in the second insulating layer, and forming a second interconnect on the second insulating layer and electrically coupled to the p-type region of the polysilicon layer by a second via formed in the second insulating layer.

2. The method according to claim 1, further comprising:

depositing a channel layer over at least one buffer layer; and

depositing a barrier layer over the channel layer.

3. The method according to claim 2, wherein the step of forming the gate structure comprises:

depositing a p-type GaN layer over the barrier layer;

depositing a gate metal on the p-type GaN layer;

forming a photoresist over the gate metal; and

etching the gate metal and the p-type GaN layer.

4. The method according to claim 3, further comprising:

etching the first insulating layer to form a pair of contact windows in the first insulating layer on opposite sides of the gate structure;

forming a source metal and a drain metal in the pair of contact windows, respectively; and

connecting the source metal to the first interconnect, and connecting the drain metal to the second interconnect, by respective vias through the second insulating layer.

5. The method according to claim 1, further comprising:

depositing a third insulating layer on the first metal interconnect and the second interconnect;

forming a plurality of vias in the third insulating layer; and

forming a pair of metal contacts on the third insulating layer and electrically coupled to the plurality of vias.

6. The method according to claim 1, wherein the step of doping the polysilicon layer further comprises leaving at least one region of the polysilicon layer undoped.

7. The method according to claim 6, wherein the undoped region of the polysilicon layer is electrically connected to the second interconnect by an additional via.

8. The method according to claim 1, wherein the first and second interconnects are formed of metal.