Semiconductor device

• US 9,837,531 B2
• Filed: 07/26/2016
• Issued: 12/05/2017
• Est. Priority Date: 12/25/2008
• Status: Active Grant

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Nakano, Yuki, Nakamura, Ryota
• Primary Examiner(s): Erdem, Fazli
• Application Number:
  US15/220,367
• Publication Number:
  US 20160336441A1
• Time in Patent Office: 497 Days
• CPC Class Codes: H01L 21/046 using ion implantation
• CPC Class Codes: H01L 21/0485 Ohmic electrodes
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.

Claims

1. A semiconductor device comprising:

a semiconductor layer made of SiC, the semiconductor layer having a front surface and a back surface;

a transistor element having an impurity region formed in a front surface portion of the semiconductor layer;

a first contact wiring formed on a back surface portion of the semiconductor layer, the first contact wiring defining one electrode electrically connected to the transistor element; and

a second contact wiring formed on the front surface portion of the semiconductor layer, the second contact wiring defining another electrode electrically connected to the transistor element;

wherein

the first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer, the second wiring layer having no silicide portion and having a resistivity lower than that of the first wiring layer, and

the second contact wiring has a third wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a fourth wiring layer formed on the third wiring layer and having a resistivity lower than that of the third wiring layer.

2. The semiconductor device according to claim 1, wherein the first wiring layer includes a polysilicon layer.

3. The semiconductor device according to claim 1, wherein the transistor element includes a MISFET having a source, a drain and a gate.

4. The semiconductor device according to claim 3, wherein the first contact wiring includes a drain electrode electrically connected to the drain.

5. The semiconductor device according to claim 1, wherein the first wiring layer has a thickness of 1000 Å

to 2000 Å

and the second wiring layer has a thickness of 0.5 μ

m to 1 μ

m.

6. The semiconductor device according to claim 1, wherein the transistor element includes

a source region formed in the front surface portion of the semiconductor layer;

a body region formed in the semiconductor layer such that the body region is in contact with the source region; and

a drain region formed in the back surface portion of the semiconductor layer such that the drain region is in contact with the body region,

the semiconductor device further comprising a source trench penetrating the source region and the body region from the front surface of the semiconductor layer,

wherein the second contact wiring is formed into the source trench.

7. The semiconductor device according to claim 6, wherein

the body region includes a body contact region formed on a side surface of the source trench, and

the third wiring layer of the second contact wiring is in contact with the drain region, the body contact region and the source region in the source trench.

8. The semiconductor device according to claim 6, wherein the source trench is U-shaped in a cross-sectional view and has a side surface and a bottom surface that are continuous through a bent surface.

9. The semiconductor device according to claim 6, wherein the fourth wiring layer of the second contact wiring is planarized.

10. The semiconductor device according to claim 6, wherein the semiconductor device further comprises:

a gate trench penetrating the source region and the body region from the front surface of the semiconductor layer;

a gate insulating film formed on an inner surface of the gate trench; and

a gate electrode embedded in the gate trench on the gate insulating film.

11. The semiconductor device according to claim 10, wherein the source trench is deeper than the gate trench.

12. The semiconductor device according to claim 10, wherein the gate insulating film includes a first portion on a bottom surface of the gate trench and a second portion on a side surface of the gate trench, and

a ratio of a thickness of the first portion to a thickness of the second portion (the first portion/the second portion) is 0.1 to 0.8.

13. The semiconductor device according to claim 1, wherein the first wiring layer includes a polysilicon layer having an impurity concentration of 10¹⁹ cm⁻

3 to 10²¹ cm<sup>−

3</sup>.

14. The semiconductor device according to claim 1, wherein

the first wiring layer includes a polysilicon layer,

the second wiring layer includes a metal layer,

the first contact wiring further includes a layer containing Ti between the polysilicon layer and the metal layer.

15. The semiconductor device according to claim 1, wherein

the third wiring layer includes a polysilicon layer,

the fourth wiring layer includes a metal layer,

the second contact wiring further includes a layer containing Ti between the polysilicon layer and the metal layer.

16. The semiconductor device according to claim 14, wherein

the metal layer includes a layer containing Al, and

the layer containing Ti includes a laminating structure of Ti and TiN which are laminated in this order from the polysilicon layer.

17. The semiconductor device according to claim 1, wherein the first wiring layer includes a polysilicon layer containing at least one conductive impurity selected from the group of conductive impurities consisting of B, P, Al and N.

18. The semiconductor device according to claim 1, wherein the front surface of the semiconductor layer is an Si surface and the back surface of the semiconductor layer is a C surface.