Semiconductor device

• US 9,837,540 B2
• Filed: 08/31/2015
• Issued: 12/05/2017
• Est. Priority Date: 07/20/2015
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Liou, En-Chiuan, Weng, Tang-Chun, Chen, Chien-Hao
• Primary Examiner(s): DINKE, BITEW A
• Application Number:
  US14/841,628
• Publication Number:
  US 20170025540A1
• Time in Patent Office: 827 Days
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing layer is disposed on sidewalls of the trench, wherein the spacing layer has a top surface lower than a top surface of the fin shaped structures. The dummy gate structure is disposed on the fin shaped structures and across the trench.

Claims

1. A semiconductor device, comprising:

a plurality of fin shaped structures disposed on a substrate;

a trench disposed between the fin shaped structures;

a shallow trench disposed in the substrate and surrounding the fin shaped structures,

a liner disposed on sidewalls of the trench and the shallow trench;

an insulating layer filled in the trench and the shallow trench, wherein the liner is between the fin shaped structures and the insulating layer in the shallow trench;

a spacing layer disposed on the sidewalls of the trench, the spacing layer being between the insulating layer and the fin shaped structures, the liner being between the spacing layer and the insulating layer in the trench, and a top surface of the liner is lower than a top surface of the fin shaped structure, wherein a top surface and a bottom surface of the sidewalls of the trench are uncovered by the spacing layer, two opposite sidewalls of the spacing layer are aligned with the top surface and the bottom surface respectively, and a top surface of the spacing layer is lower than the top surface of the fin shaped structure; and

a dummy gate structure disposed on the fin shaped structures and across the trench.

2. The semiconductor device of claim 1, wherein the trench comprises tipped sidewalls.

3. The semiconductor device of claim 1, wherein the spacing layer only contacts the sidewalls of the trench.

4. The semiconductor device of claim 1, wherein the liner is disposed on the spacing layer.

5. The semiconductor device of claim 4, wherein the liner has a shoulder portion in the trench.

6. The semiconductor device of claim 1, wherein the dummy gate structure has a portion disposed in the trench.

7. The semiconductor device of claim 1, wherein the trench comprises a stepped sidewall and the spacing layer is disposed on a stepped portion of the stepped sidewall.

8. The semiconductor device of claim 1, wherein the dummy gate structure comprises a gate dielectric layer contacting the top surface of the sidewalls, and a spacer surrounded the gate dielectric layer and not directly contacted the spacing layer.