Semiconductor device having an oxide semiconductor layer

• US 9,837,544 B2
• Filed: 01/05/2016
• Issued: 12/05/2017
• Est. Priority Date: 07/02/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US14/988,628
• Publication Number:
  US 20160211380A1
• Time in Patent Office: 700 Days
• Field of Search: 257 43, 257 57, 257 66, 257 67, 257 68, 257 71, 438152, 438161
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/2206 Amorphous materials
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous

Abstract

A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.

Claims

1. A semiconductor device comprising:

an oxide semiconductor layer over an insulating layer;

a first metal oxide layer on and in contact with the oxide semiconductor layer;

a second metal oxide layer on and in contact with the oxide semiconductor layer;

a first metal nitride layer on the first metal oxide layer, wherein the first metal oxide layer extends beyond an inner side edge of the first metal nitride layer;

a second metal nitride layer on the second metal oxide layer, wherein the second metal oxide layer extends beyond an inner side edge of the second metal nitride layer;

a gate insulating layer over the first metal nitride layer, the second metal nitride layer and the oxide semiconductor layer; and

a gate electrode layer over the gate insulating layer, the gate electrode layer overlapping with the oxide semiconductor layer,

wherein inner side edges of the first metal oxide layer and the second metal oxide layer are tapered.

2. The semiconductor device according to claim 1, wherein each of the first metal nitride layer and the second metal nitride layer comprises titanium nitride, molybdenum nitride or tungsten nitride.

3. The semiconductor device according to claim 1, wherein each of the first metal oxide layer and the second metal oxide layer comprises a material selected from the group consisting of indium oxide, indium tin oxide and indium zinc oxide.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises at least one element selected from In, Ga, Sn, Zn, Al, Mg, Hf, and lanthanoid.

5. The semiconductor device according to claim 1, wherein the gate insulating layer contains oxygen.

6. The semiconductor device according to claim 1, wherein a taper angle of the inner side edges of the first metal oxide layer and the second metal oxide layer is smaller than a taper angle of the inner side edges of the first metal nitride layer and the second metal nitride layer.

7. The semiconductor device according to claim 1, wherein the first metal oxide layer and the second metal oxide layer comprise a material selected from titanium oxide, titanium niobium oxide, molybdenum oxide, tungsten oxide, magnesium oxide, calcium oxide, and gallium oxide.

8. The semiconductor device according to claim 1, wherein the gate electrode layer overlaps with the first metal nitride layer and the second metal nitride layer.

9. A semiconductor device comprising:

an oxide semiconductor layer over an insulating layer;

a first metal oxide layer on and in contact with the oxide semiconductor layer;

a second metal oxide layer on and in contact with the oxide semiconductor layer;

a first metal nitride layer on the first metal oxide layer, wherein the first metal oxide layer extends beyond an inner side edge of the first metal nitride layer;

a second metal nitride layer on the second metal oxide layer, wherein the second metal oxide layer extends beyond an inner side edge of the second metal nitride layer;

a gate insulating layer over the first metal nitride layer, the second metal nitride layer and the oxide semiconductor layer; and

a gate electrode layer over the gate insulating layer, the gate electrode layer overlapping with the oxide semiconductor layer,

wherein inner side edges of the first metal oxide layer and the second metal oxide layer are tapered, and

wherein a surface portion of the oxide semiconductor layer between the first metal oxide layer and the second metal oxide layer is etched.

10. The semiconductor device according to claim 9, wherein each of the first metal nitride layer and the second metal nitride layer comprises titanium nitride, molybdenum nitride or tungsten nitride.

11. The semiconductor device according to claim 9, wherein each of the first metal oxide layer and the second metal oxide layer comprises a material selected from the group consisting of indium oxide, indium tin oxide and indium zinc oxide.

12. The semiconductor device according to claim 9, wherein the oxide semiconductor layer comprises at least one element selected from In, Ga, Sn, Zn, Al, Mg, Hf, and lanthanoid.

13. The semiconductor device according to claim 9, wherein the gate insulating layer contains oxygen.

14. The semiconductor device according to claim 9, wherein a taper angle of the inner side edges of the first metal oxide layer and the second metal oxide layer is smaller than a taper angle of the inner side edges of the first metal nitride layer and the second metal nitride layer.

15. The semiconductor device according to claim 9, wherein the first metal oxide layer and the second metal oxide layer comprise a material selected from titanium oxide, titanium niobium oxide, molybdenum oxide, tungsten oxide, magnesium oxide, calcium oxide, and gallium oxide.

16. The semiconductor device according to claim 9, wherein the gate electrode layer overlaps with the first metal nitride layer and the second metal nitride layer.

17. A semiconductor device comprising:

an oxide semiconductor layer over an insulating layer;

a first metal oxide layer on and in contact with the oxide semiconductor layer;

a second metal oxide layer on and in contact with the oxide semiconductor layer;

a first metal layer on the first metal oxide layer, wherein the first metal oxide layer extends beyond an inner side edge of the first metal layer;

a second metal layer on the second metal oxide layer, wherein the second metal oxide layer extends beyond an inner side edge of the second metal layer;

a gate insulating layer over the first metal layer, the second metal layer and the oxide semiconductor layer; and

a gate electrode layer over the gate insulating layer, the gate electrode layer overlapping with the oxide semiconductor layer,

wherein a taper angle of inner side edges of the first metal oxide layer and the second metal oxide layer is smaller than a taper angle of the inner side edges of the first metal layer and the second metal layer.

18. The semiconductor device according to claim 17, wherein each of the first metal layer and the second metal layer comprises copper.

19. The semiconductor device according to claim 17, wherein each of the first metal oxide layer and the second metal oxide layer comprises a material selected from the group consisting of indium oxide, indium tin oxide and indium zinc oxide.

20. The semiconductor device according to claim 17, wherein the oxide semiconductor layer comprises at least one element selected from In, Ga, Sn, Zn, Al, Mg, Hf, and lanthanoid.

21. The semiconductor device according to claim 17, wherein the gate insulating layer contains oxygen.

22. The semiconductor device according to claim 17, wherein the first metal oxide layer and the second metal oxide layer comprise a material selected from titanium oxide, titanium niobium oxide, molybdenum oxide, tungsten oxide, magnesium oxide, calcium oxide, and gallium oxide.

23. The semiconductor device according to claim 17, wherein the gate electrode layer overlaps with the first metal layer and the second metal layer.

24. A semiconductor device comprising:

an oxide semiconductor layer over an insulating layer;

a first metal oxide layer on and in contact with the oxide semiconductor layer;

a second metal oxide layer on and in contact with the oxide semiconductor layer;

a first metal layer on the first metal oxide layer, wherein the first metal oxide layer extends beyond an inner side edge of the first metal layer;

a second metal layer on the second metal oxide layer, wherein the second metal oxide layer extends beyond an inner side edge of the second metal layer;

a gate insulating layer over the first metal layer, the second metal layer and the oxide semiconductor layer; and

a gate electrode layer over the gate insulating layer, the gate electrode layer overlapping with the oxide semiconductor layer,

wherein a taper angle of inner side edges of the first metal oxide layer and the second metal oxide layer is smaller than a taper angle of the inner side edges of the first metal layer and the second metal layer, and

wherein a surface portion of the oxide semiconductor layer between the first metal oxide layer and the second metal oxide layer is etched.