Standby voltage condition for fast RF amplifier bias recovery

• US 9,837,965 B1
• Filed: 09/16/2016
• Issued: 12/05/2017
• Est. Priority Date: 09/16/2016
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Wagh, Poojan, Pal, Kashish
• Primary Examiner(s): Nguyen, Patricia T
• Application Number:
  US15/268,297
• Time in Patent Office: 445 Days
• Field of Search: 330311, 330296
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/249 A switch coupled in the input circuit of an amplifier being controlled by a circuit, e.g. feedback circuitry being controlling the switch
• CPC Class Codes: H03F 2200/453 Controlling being realised by adding a replica circuit or by using one among multiple identical circuits as a replica circuit
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence

Abstract

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

Claims

1. A circuital arrangement comprising:

a transistor stack configured to operate as an amplifier, the transistor stack comprising a plurality of stacked transistors comprising an input transistor and an output transistor, the transistor stack configured to operate between a first supply voltage coupled to the output transistor and a reference voltage coupled to the input transistor; and

a biasing circuit comprising a replica circuit of the transistor stack, the biasing circuit configured to provide an input gate biasing voltage to the input transistor and to a corresponding first transistor of the replica circuit, the replica circuit configured to operate between a second supply voltage coupled to a last transistor of the replica circuit in correspondence of the output transistor, and the reference voltage coupled to the first transistor;

wherein the circuital arrangement is configured to operate in at least a first mode and a second mode,

wherein during operation in the first mode, the biasing circuit;

couples the last transistor of the replica circuit to the second supply voltage through a reference current source that generates a reference current, and

regulates the input gate biasing voltage so as the reference current is conducted through the replica circuit, and

wherein during operation in the second mode, the biasing circuit;

sets the input gate biasing voltage to a voltage so as essentially no current is conducted though the replica circuit,

deactivates the reference current source, and

resistively couples the last transistor of the replica circuit to the second supply voltage.

2. The circuital arrangement according to claim 1, wherein biasing voltages provided to gates of transistors of the replica circuit during operation in the first mode are substantially equal to biasing voltages provided to gates of transistors of the replica circuit during operation in the second mode.

3. The circuital arrangement according to claim 2, wherein voltages at common source-drain nodes of the replica circuit during operation in the first mode are within 0.5 V of respective voltages during operation in the second mode.

4. The circuital arrangement according to claim 1, wherein the biasing circuit further comprises a switch, the switch selectively coupling the second supply voltage to the last transistor of the replica circuit.

5. The circuital arrangement according to claim 4, wherein:

during operation in the first mode, the last transistor is coupled to the current source through the switch, and

during operation in the second mode, the last transistor is coupled to the second supply voltage through the switch.

6. The circuital arrangement according to claim 1, wherein gates of transistors of the replica circuit and gates of the plurality of transistors of the transistor stack are provided with same biasing voltages.

7. The circuital arrangement according to claim 1, wherein gates of transistors of the replica circuit and gates of the plurality of transistors of the transistor stack are provided with different biasing voltages.

8. The circuital arrangement according to claim 1, wherein a height of a transistor stack of the replica circuit is equal to a height of the transistor stack configured to operate as an amplifier.

9. The circuital arrangement according to claim 1, wherein a height of a transistor stack of the replica circuit is different form a height of the transistor stack configured to operate as an amplifier.

10. The circuital arrangement according to claim 1, wherein transistors of the replica circuit and the plurality of transistors of the transistor stack are floating transistors.

11. The circuital arrangement according to claim 1, wherein transistors of the replica circuit and the plurality of transistors of the transistor stack are body tied transistors.

12. The circuital arrangement according to claim 1, wherein transistors of the replica circuit and/or the plurality of transistors of the transistor stack comprise a combination of body tied transistors and floating transistors.

13. The circuit arrangement according to claim 1, further comprising one or more gate capacitors each connected between a gate of a transistor of the plurality of stacked transistors except the input transistor, wherein the each gate capacitor is configured to allow a gate voltage at the gate to vary along with a radio frequency (RF) voltage at a drain of the transistor.

14. The circuital arrangement according to claim 13, wherein the one or more gate capacitors are configured to substantially equalize an output RF voltage at a drain of the output transistor across the plurality of stacked transistors.

15. The circuital arrangement according to claim 1, wherein the input gate biasing voltage during operation in the second mode is substantially equal to the reference voltage.

16. A method for biasing a transistor stack configured to operate as an amplifier using a replica circuit of the transistor stack, the method comprising:

during a first mode of operation of the amplifier;

generating a reference current through a current source;

coupling, through the current source, a supply voltage to the replica circuit;

regulating a biasing voltage of an input transistor of the transistor stack;

based on the regulating, conducting the reference current though the replica circuit; and

during a second mode of operation of the amplifier;

setting the biasing voltage to a fixed value so as essentially no current is conducted through the replica circuit;

deactivating the current source; and

resistively coupling the supply voltage to the replica circuit.

17. The method according to claim 16, wherein biasing voltages provided to gates of transistors of the replica circuit during operation in the first mode are substantially equal to biasing voltages provided to gates of transistors of the replica circuit during operation in the second mode.

18. The method according to claim 17, wherein voltages at common source-drain nodes of the replica circuit during operation in the first mode are within 0.5 V of respective voltages during operation in the second mode.