Control of a tank circuit in a wireless power transmission system providing FSK communication

• US 9,838,084 B2
• Filed: 09/30/2014
• Issued: 12/05/2017
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Khandelwal, Ashish, Neidorff, Robert A.
• Primary Examiner(s): Chang, Joseph
• Application Number:
  US14/502,285
• Publication Number:
  US 20160094278A1
• Time in Patent Office: 1,162 Days
• Field of Search: 307104
• CPC Class Codes: H01F 38/14 Inductive couplings for wireless supply or distribution of electric power using inductive coupling H02J50/10
• CPC Class Codes: H02J 50/10 using inductive coupling
• CPC Class Codes: H02J 50/80 involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
• CPC Class Codes: H04B 5/79 for data transfer in combination with power transfer
• CPC Class Codes: H04L 27/10 Frequency-modulated carrier systems, i.e. using frequency-shift keying H04L27/32 takes precedence

Abstract

A transmitter circuit in a wireless power transmission system has a tank circuit, having an inductor and a capacitor, the inductor being couplable to the inductor of a receiver circuit. An oscillator generates an oscillation frequency signal for driving the tank circuit. A first digital-to-analog converter (DAC) provides a first control signal to control the oscillating frequency of the oscillator. A frequency shift keying (FSK) circuit changes a digital signal input to the digital-to-analog converter for shifting the oscillation frequency utilized to drive the tank circuit, the FSK signal transmitting data or commands to the receiver circuit. A method of transmitting FSK signals in a wireless power transmission system is also disclosed.

Claims

1. An oscillator circuit comprising:

(a) a mode input, a clock input, and a down/up input;

(b) a first up/down counter having an up input, a down input and parallel bit outputs;

(c) a second up/down counter having an up input, a down input and parallel bit outputs;

(d) gating circuits having inputs and outputs coupling the mode input and down/up input to the first and second up/down counters;

(e) a first digital to analog converter having inputs coupled to the parallel bit outputs of the first up/down counter and having a frequency voltage reference output;

(f) a second digital to analog converter having inputs coupled to the parallel bit outputs of the second up/down counter and having a duty cycle voltage reference output;

(g) oscillator circuitry having a frequency input coupled to the output frequency voltage reference output, a duty cycle input coupled to the duty cycle voltage reference output, a frequency output, and a duty cycle output.

2. The oscillator circuit of claim 1 in which the first up/down counter is an 8 bit counter having 8 parallel bit outputs.

3. The oscillator circuit of claim 1 in which the second up/down counter is a 6 bit counter having 6 parallel bit outputs.

4. The oscillator circuit of claim 1 in which the gating circuit includes AND gates with inverting and non-inverting inputs.

5. The oscillator circuit of claim 1 including a PWN CNTL input coupled to an input of the gating circuits.

6. The oscillator circuit of claim 1 including a PWM1/CLK node, a first driver node, a PWM2/NUP node, a second driver node, and a PWN CNTL input causing the first driver node to switch between the frequency output and the PWM1/CLK nod and causing the second driver node to switch between the PWM2/DNUP node and the duty cycle output.

7. An oscillator circuit comprising:

(a) a dual ramp oscillator having a constant current source generating ramp signals through a first series connection of a first switch and first capacitor, a second series connection of a second switch and second capacitor, a third switch in parallel to the first capacitor to ground, and a fourth switch in parallel to the second capacitor to ground, the first and fourth switches having an S1 input and the second and third switches having an S2 input;

(b) a first comparator having a first input, a second input connected to between the first switch, the first capacitor, and the third switch, a third input connected to between the second switch, the second capacitor, and the fourth switch, and an output;

(c) a second comparator having a first input, a second input connected to between the first switch, the first capacitor, and the third switch, and a PW1 output;

(d) a third comparator having a first input, a second input connected to between the second switch, the second capacitor, and the fourth switch, and a PW2 output;

(e) a first gate having an S1 input, an input connected to the PW1 output, and a PWM1 output;

(f) a second gate having an S2 input, an input connected to the PW2 output, and a PWM2 output; and

(g) a differential output circuit having an input coupled to the output of the first comparator, an S1 output connected to the S1 inputs and an S2 output connected to the S2 inputs.

8. The oscillator circuit of claim 7 in which the first input of the first comparator is a frequency voltage reference input.

9. The oscillator circuit of claim 7 in which the first inputs of the second and third comparators are duty cycle voltage reference inputs.

10. The oscillator circuit of claim 7 including a flip flop having an input connected to the output of the first comparator and an output connected to the input of the differential output circuit.

11. The oscillator circuit of claim 7 including a D-type flip flop having a clock input connected to the output of the first comparator, a D input, and an inverting output connected to the D input and the input of the differential output circuit.

12. A process of controlling an oscillator circuit comprising;

(a) producing a frequency voltage reference output from a first digital to analog converter;

(b) producing a pulse width voltage reference output from a second digital to analog converter;

(c) producing a first switch signal from the frequency voltage reference output;

(d) producing a first pulse width signal from the pulse width voltage reference output; and

(e) gating the first pulse width signal with the first switch signal to control the pulse width of an output signal.