Battery, battery controller, and method for the secured digital transmission of current measurement values

• US 9,841,798 B2
• Filed: 10/09/2014
• Issued: 12/12/2017
• Est. Priority Date: 10/24/2013
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Butzmann, Stefan, Bergmann, Sven
• Primary Examiner(s): Rizk, Sam
• Application Number:
  US15/030,654
• Publication Number:
  US 20160259386A1
• Time in Patent Office: 1,160 Days
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: G06F 11/0736 in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function testing or monitoring of automated control systems G05B23/02
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G08C 25/00 Arrangements for preventing or correcting errors; Monitoring arrangements
• CPC Class Codes: H04L 12/40 Bus networks
• CPC Class Codes: H04L 2012/40215 Controller Area Network CAN
• CPC Class Codes: H04L 2012/40234 Local Interconnect Network LIN
• CPC Class Codes: H04L 2012/40273 the transportation system being a vehicle
• CPC Class Codes: H04L 25/4915 using pattern inversion or substitution H04L25/4908 takes precedence
• CPC Class Codes: H04Q 2209/30 using a wired architecture
• CPC Class Codes: H04Q 9/00 Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom

Abstract

The invention relates to a method for the secured digital transmission of current measurement values and to a battery (1) and a battery controller (10) which are suitable for carrying out the method. The method has the steps of detecting (S1, S2) an amplitude of a battery current (I_B) in a battery (1) using a first and a second sensor (2, 3), generating (S3, S4) a first and a second bit sequence, each of which describes the detected amplitude, generating a mirrored second bit sequence (21) by reversing (S5) a sequence of the bits provided by the second bit sequence (20), simultaneously transmitting (S6) the first bit sequence via a first data bus (5) and the mirrored second bit sequence (21) via a second data bus (6) to a battery controller (10), generating a second bit sequence (20) by reversing (S7) a sequence of the bits provided by the mirrored second bit sequence (21) after the simultaneous transmission (S6), and finally detecting (S8) a possible error in the first bit sequence or the second bit sequence (20) by comparing the first bit sequence (20) with the second bit sequence (21). Transmission faults are thus detected in particular in a transmission path between the sensors of the battery and the battery controller, said faults being caused by a common disturbance. Additionally, faults can also be detected which are caused by a disturbance that only affects one of the sensors or a part of the transmission path.

Claims

1. A battery (1) having a device for the digital transmission of current measurement values, comprising:

a first sensor (2) for detecting an amplitude of a battery current (I_B) and which generates a first bit sequence which describes the amplitude detected using the first sensor (2);

a second sensor (3) for detecting the amplitude of the battery current (I_B) and which generates a second bit sequence (20) which describes the amplitude detected using the second sensor (3);

a mirroring unit (4) coupled to the second sensor (3) such that the second bit sequence (20) is transmitted from the second sensor (3) to said mirroring unit and which generates a mirrored second bit sequence (21) by reversing a sequence of the bits provided by the second bit sequence (20), wherein a first bit of the second bit sequence (20) becomes a last bit of the mirrored second bit sequence (21) and a last bit of the second bit sequence (20) becomes a first bit of the mirrored second bit sequence (21); and

a transmission interface (7) which is equipped to facilitate a simultaneous coupling of the first bit sequence from the first sensor (2) into a first data bus (5) and the mirrored second bit sequence (21) from the mirroring unit (4) into a second data bus (6).

2. The battery according to claim 1, characterized in that the first sensor (2) and the second sensor (3) are identically constructed sensors with regard to detecting the amplitude of the battery current (I_B) and generating the bit sequence.

3. The battery according to claim 1, characterized in that the first data bus (5) and/or the second data bus (6) is a LIN bus or a CAN bus.

4. The battery according to claim 1, characterized in that the first sensor (2) and/or the second sensor (3) comprise(s) a Hall sensor or a shunt-based sensor.

5. The battery according to claim 1, wherein the second sensor (3) comprises the mirroring unit (4).

6. A battery controller (10) having a device for receiving a digital transmission of current measurement values, comprising:

a receiving interface (11) which decouples a first bit sequence from the a first data bus (5) and simultaneously decouples a mirrored second bit sequence (21) from a second data bus (6);

an anti-mirroring unit (12) which generates a second bit sequence (20) by reversing a sequence of the bits provided by the mirrored second bit sequence (21), wherein a first bit of the mirrored second bit sequence (21) becomes a last bit of the second bit sequence (20) and a last bit of the mirrored second bit sequence (21) becomes a first bit of the second bit sequence (20); and

a control unit (13) which is equipped to detect a possible error in the first bit sequence or the second bit sequence (20) by comparing the first bit sequence with the second bit sequence (20).

7. The battery controller according to claim 6, characterized in that the control unit (13) is equipped to detect a possible error in the first bit sequence or the second bit sequence (20) by a bitwise comparison of the first bit sequence with the second bit sequence (20).

8. The battery controller according to claim 6, characterized in that the control unit (13) is equipped:

to generate a first analogous value from the first bit sequence and to generate a second analogous value from the second bit sequence (20); and

to detect a possible error in the first bit sequence or the second bit sequence (20) by comparing the first analogous value with the second analogous value.

9. The battery controller (10) according to claim 6, characterized in that the first data bus (5) and/or the second data bus (6) is/are a LIN bus or a CAN bus.

10. A method for the secured digital transmission of current measurement values, the method comprising:

detecting (S1) an amplitude of a battery current (I_B) in a battery (1) using a first sensor (2);

detecting (S2) the amplitude of the battery current (I_B) in the battery (1) using a second sensor (3);

generating (S3) a first bit sequence which describes the amplitude detected using the first sensor (2);

generating (S4) a second bit sequence which describes the amplitude detected using the second sensor (3);

generating (S5) a mirrored second bit sequence (21) by reversing a sequence of the bits provided by the second bit sequence, wherein a first bit of the second bit sequence (20) becomes a last bit of the mirrored second bit sequence (21) and a last bit of the second bit sequence (20) becomes a first bit of the mirrored second bit sequence (21);

simultaneously transmitting (S6) the first bit sequence via a first data bus (5) to a battery controller (10) and the mirrored second bit sequence (21) via a second data bus (6) to the battery controller (10);

generating (S7) the second bit sequence (20) by reversing a sequence of the bits provided by the mirrored second bit sequence, wherein a first bit of the mirrored second bit sequence (21) becomes a last bit of the second bit sequence (20) and a last bit of the mirrored second bit sequence (21) becomes a first bit of the second bit sequence (20); and

detecting (S8) a possible error in the first bit sequence or the second bit sequence (20) by comparing the first bit sequence with the second bit sequence (20).