Microarchitecture for floating point fused multiply-add with exponent scaling

• US 9,841,948 B2
• Filed: 08/12/2015
• Issued: 12/12/2017
• Est. Priority Date: 08/30/2012
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Wang, Liang-Kai
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US14/824,547
• Publication Number:
  US 20150347089A1
• Time in Patent Office: 853 Days
• Field of Search: None
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00

Abstract

Systems and methods for implementing a floating point fused multiply and accumulate with scaling (FMASc) operation. A floating point unit receives input multiplier, multiplicand, addend, and scaling factor operands. A multiplier block is configured to multiply mantissas of the multiplier and multiplicand to generate an intermediate product. Alignment logic is configured to pre-align the addend with the intermediate product based on the scaling factor and exponents of the addend, multiplier, and multiplicand, and accumulation logic is configured to add or subtract a mantissa of the pre-aligned addend with the intermediate product to obtain a result of the floating point unit. Normalization and rounding are performed on the result, avoiding rounding during intermediate stages.

Claims

1. A non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations for executing a floating point operation, the non-transitory computer-readable storage medium comprising:

code for causing a floating point unit to receive multiplier, multiplicand, addend, and scaling factor operands;

code for causing a multiplier block to perform a partial multiplication operation on mantissas of the multiplier and multiplicand operands to obtain an intermediate product;

code for causing a pre-alignment block to pre-align a mantissa of the addend operand with the intermediate product based on the scaling factor operand and exponents of the addend, multiplier, and multiplicand operands; and

code for causing an accumulator block to add or subtract the mantissa of the pre-aligned addend operand and the intermediate product to obtain the result of the floating point operation.

2. The non-transitory computer-readable storage medium of claim 1, further comprising code for causing a normalization block to normalize the result.

3. The non-transitory computer-readable storage medium of claim 1, further comprising code for causing a rounding block to perform a rounding operation on the normalized result, wherein rounding is avoided before the normalized result is obtained.

4. A non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations for performing a floating point scaled fused multiply and accumulate (FMASc) operation, the non-transitory computer-readable storage medium comprising:

code for causing a multiplier block to multiply mantissas of a floating point multiplier operand with a floating point multiplicand operand to obtain a mantissa of a product;

code for causing a leading zero count (LZC) block to determine a count of the number of leading zeros of the mantissa of a floating point addend operand;

code for causing a pre-alignment block to determine a pre-alignment shift value for the floating point addend operand based on the LZC, a scaling factor operand, and exponents of the floating point addend operand, the floating point multiplier operand, and the floating point multiplicand operand;

code for causing an alignment block to shift the mantissa of the floating point addend operand with the pre-alignment shift value to obtain a pre-aligned addend;

code for causing an accumulator block to accumulate the mantissa of the product and the pre-aligned addend to obtain an intermediate result;

code for causing a leading zero anticipator block to determine the number of leading zeros of the intermediate result;

code for causing a normalization block to determine a normalizing shift value based on the pre-alignment shift value and the number of leading zeros of the intermediate result; and

code for causing the normalization block to normalize the intermediate result based on the normalizing shift value in a normalization block to obtain a normalized output of the FMASc operation.

5. The non-transitory computer-readable storage medium of claim 4 further comprising code for causing a rounding block to round the normalized output with a rounding value based on the normalizing shift value.

6. The non-transitory computer-readable storage medium of claim 5, wherein the normalizing shift value is one of a left shift or a right shift.

7. The non-transitory computer-readable storage medium of claim 6, wherein the left shift is based on the number of leading zeros of the intermediate result or a function of exponents of the floating point addend operand, the floating point multiplier operand, and the floating point multiplicand operand.

8. The non-transitory computer-readable storage medium of claim 6, wherein the right shift is based on a function of the scaling factor operand, and exponents of the floating point addend operand, the floating point multiplier operand, and the floating point multiplicand operand.

9. The non-transitory computer-readable storage medium of claim 4, wherein the accumulating is one of an adding or subtracting, as specified by the FMASc operation.

10. A non-transitory computer-readable storage medium comprising code, which, when executed by a processor, causes the processor to perform operations for executing a floating point operation, the non-transitory computer-readable storage medium comprising:

code for causing a floating point unit to receive multiplier, multiplicand, addend, and scaling factor operands;

code for causing a multiplier block to perform a partial multiplication operation on mantissas of the multiplier and multiplicand operand to obtain an intermediate product;

code for causing a pre-alignment block to pre-align a mantissa of the addend with the intermediate product based on the scaling factor and exponents of the addend, multiplier, and multiplicand; and

code for causing an accumulator block to accumulate the mantissa of the pre-aligned addend and the intermediate product in an accumulator block to obtain the result of the floating point operation.

11. The non-transitory computer-readable storage medium of claim 10, further comprising code for causing a normalization block to normalize the result.

12. The non-transitory computer-readable storage medium of claim 11, further comprising code for causing a rounding block to perform a rounding operation on the normalized result, wherein rounding is avoided before the normalized result is obtained.

13. The non-transitory computer-readable storage medium of claim 10, wherein the accumulation is one of an adding or subtracting, as specified by the floating point operation.