Renaming with generation numbers

• US 9,841,974 B2
• Filed: 10/31/2014
• Issued: 12/12/2017
• Est. Priority Date: 04/25/2014
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Wilson, Sophie, Redford, John, Kurd, Tariq
• Primary Examiner(s): Caldwell, Andrew
• Assistant Examiner(s): Mehta, Jyoti
• Application Number:
  US14/530,111
• Publication Number:
  US 20150309796A1
• Time in Patent Office: 1,138 Days
• CPC Class Codes: G06F 9/30098 Register arrangements
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3842 Speculative instruction execution

Abstract

A processor including a register file having a plurality of registers, and configured for out-of-order instruction execution, further includes a renamer unit that produces generation numbers that are associated with register file addresses to provide a renamed version of a register that is temporally offset from an existing version of that register rather than assigning a non-programmer-visible physical register as the renamed register.

Claims

1. An apparatus comprising:

a register, addressed by a register address, configured to store a value;

a renamer configured to receive the register address and an indication of whether the register is a destination or a source for a fetched instruction and generate an inflight generation number associated with the register for the fetched instruction; and

a reservation queue, communicatively coupled with the register and the renamer, configured to concurrently store the register address and the inflight generation number.

2. The apparatus of claim 1, wherein the reservation queue is further configured to store an instruction opcode of the fetched instruction.

3. The apparatus of claim 1, wherein the register and the renamer are configured to provide data to the reservation queue concurrently.

4. The apparatus of claim 1, wherein the renamer is further configured to store an inflight array that indicates which generation of the register is currently being used.

5. The apparatus of claim 4, wherein the renamer is further configured to maintain a true pointer that indicates a latest confirmed returned generation of the register.

6. The apparatus of claim 5, wherein the renamer is further configured to generate a valid bit indicating whether a value associated with the inflight generation number is valid based, at least in part on, the inflight array and the true pointer.

7. The apparatus of claim 6, wherein the reservation queue is further configured to store a value and the valid bit responsive to the register being a source register for the fetched instruction.

8. The apparatus of claim 4, wherein the renamer is further configured to maintain a Speculative Index Number (SIN) pointer that points to the inflight generation number responsive to the fetched instruction being executed speculatively.

9. The apparatus of claim 8, wherein the renamer is further configured to update a true pointer to equal the SIN pointer and clear the SIN pointer responsive to the fetched instruction being executed speculatively and confirmed.

10. The apparatus of claim 8, wherein the renamer is further configured to update the inflight array and clear the SIN pointer responsive to the fetched instruction being executed speculatively and cancelled.

11. The apparatus of claim 1, wherein to generate the inflight generation number, the renamer is configured to select a next non-inflight generation number responsive to a tick bit being set in the fetched instruction.

12. The apparatus of claim 1, wherein the renamer is further configured to receive results from the fetched instruction and a destination register address, update an inflight array, and enable the register to be updated with the results responsive to there being no further generations of the register in flight.

13. The apparatus of claim 1, wherein the renamer is further configured to update an inflight array, and the register is configured to store results of the fetched instruction if there are no later inflight generation numbers for the register.

14. The apparatus of claim 13, further comprising register write control logic, wherein the renamer is further configured to inform the register write control logic whether the results should be stored.

15. A method comprising:

receiving, by a register renamer, a register address specified by a fetched instruction;

generating, by the register renamer, an inflight register generation number based at least in part on the register address, the inflight register generation number comprising a newest inflight generation number associated with the register address when the register address is a source register address, or an inflight generation number after the newest inflight generation number associated with the register address when the register address is a destination register address;

and

providing the generated inflight register generation number to a reservation queue.

16. The method of claim 15, further comprising providing the inflight register generation number concurrently with a register file providing a value.

17. The method of claim 15, further comprising maintaining an inflight array that indicates which generations of a register are currently being used.

18. The method of claim 17, further comprising maintaining a true pointer that indicates a latest confirmed returned generation of the register.

19. The method of claim 18, further comprising generating a valid bit indicating that a value in a register file is valid based on the inflight array and the true pointer.

20. The method of claim 17, further comprising maintaining a Speculative Index Number (SIN) pointer that points to the inflight generation number associated with the fetched instruction responsive to the fetched instruction being executed speculatively.

21. The method of claim 20, further comprising updating a true pointer and clearing the SIN pointer responsive to the fetched instruction being executed speculatively and confirmed.

22. The method of claim 20, further comprising updating the inflight array and clearing the SIN pointer responsive to the fetched instruction being executed speculatively and cancelled.

23. The method of claim 15, further comprising receiving a tick bit and selecting a next non-inflight register generation number for the register address responsive to the tick bit being set in the fetched instruction.