Data processing device, method of execution error detection and integrated circuit

• US 9,842,014 B2
• Filed: 11/22/2012
• Issued: 12/12/2017
• Est. Priority Date: 11/22/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Ralston, John
• Primary Examiner(s): Butler, Sarai
• Application Number:
  US14/646,177
• Publication Number:
  US 20150293807A1
• Time in Patent Office: 1,846 Days
• Field of Search: 714 11
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/1494 N-modular type
• CPC Class Codes: G06F 11/1641 where the comparison is not performed by the redundant processing components
• CPC Class Codes: G06F 2201/835 Timestamp

Abstract

A data processing device provided with an error detection unit includes a processor arranged to support execution of an operation including a first sequence of instructions and execution of a second sequence of instructions implementing the operation, the first and second sequences of instructions generating, when in use, a first result and a second result, respectively. Configurable circuitry is also provided and arranged to support a repository to receive the first result and the second result following generation thereof. The configurable circuitry is configured as a function comparator unit arranged to compare the first and second results for consistency and to control further execution of the first implementation and the second implementation in response to a result of the comparison.

Claims

1. A data processing device provided with an error detection unit, the device comprising:

a processor arranged to support execution of an operation and configured to execute a first sequence of instructions in accordance with a first implementation of the operation and a second sequence of instructions in accordance with a second implementation of the operation, the first and second sequences of instructions generating, when executed, a first result and a second result, respectively; and

configurable circuitry arranged to support a repository to receive the first result and the second result following generation thereof;

wherein

the configurable circuitry is configured as a function comparator unit arranged to compare the first and second results for consistency and to control further execution of the first implementation and the second implementation in response to a result of the comparison, wherein the function comparator unit comprises a first watchdog timer unit arranged to police a first time period in response to an instruction to perform the operation, the first watchdog timer identifying an exception condition in response to elapse of the first time period without receipt by the repository of the first result, and the function comparator unit further comprising a second watchdog timer arranged to police a second time period in response to receipt by the repository of the first result, the second watchdog timer identifying an exception condition in response to elapse of the second time period without receipt by the repository of the second result.

2. A data processing device as claimed in claim 1, wherein the function comparator unit is arranged to permit further execution of the first and second sequences of instructions in response to receipt by the repository of the first and second results before expiry of the first time period and the second time period, respectively.

3. A data processing device as claimed in claim 1, wherein the processor comprises a core supporting sequential execution of the first sequence of instructions and the second sequence of instructions.

4. A data processing device as claimed in claim 3, wherein the function comparator unit is arranged to set a duration of the second time period to be equal to a predetermined period of time in excess of the duration of the first time period.

5. A data processing device as claimed in claim 1, wherein the processor comprises a first core supporting execution of the first sequence of instructions and a second core supporting execution of the second sequence of instructions.

6. A data processing device as claimed in claim 5, wherein the first core has a first architecture associated therewith and the second core has a second architecture associated therewith, the first and second architectures being different.

7. A data processing device as claimed in claim 1, wherein the first sequence of instructions is in accordance with a first implementation methodology and the second sequence of instructions is in accordance with a second implementation methodology.

8. A data processing device as claimed in claim 5, wherein the processor comprises a third core supporting execution of a third sequence of instructions.

9. A data processing device as claimed in claim 5, wherein the second core supports a third sequence of instructions.

10. A data processing device as claimed in claim 9, wherein the third sequence of instructions is a second instantiation of the second implementation.

11. A data processing device as claimed in claim 9, wherein the third sequence of instructions is arranged to generate a third result, the function comparator unit is arranged to compare the first, second and third results for consistency and to identify a majority of the first, second and third results that are consistent.

12. A data processing device as claimed in claim 11, wherein the function comparator unit is arranged to identify an inconsistent result from the first, second and third results and to prevent further execution of the sequence of instructions from the first, second and third implementations of the operation associated with the inconsistent result.

13. A data processing device as claimed in claim 1, wherein the first result and the second result are the results of a first input/output transaction request and a second input/output transaction request, respectively.

14. A data processing device as claimed in claim 13, wherein the function comparator unit is arranged to execute the first and second input/output transaction request in response to the first and second input/output transaction requests being determined to be consistent.

15. A data processing device as claimed in claim 1, wherein the comparison performed by the function comparator unit is relative to a predetermined threshold.

16. An integrated circuit comprising a data processing device as claimed in claim 1.

17. A method of execution error detection comprising:

supporting execution of an operation comprising a first sequence of instructions in accordance with a first algorithmic implementation of the operation and execution of a second sequence of instructions in accordance with a second algorithmic implementation of the operation;

executing the first sequence of instructions to generate a first result;

executing the second sequence of instructions to generate a second result;

receiving the first result and the second result in a repository;

using a first watchdog timer, identifying an exception condition in response to elapse of a first time period without receipt by the repository of the first result;

using a second watchdog timer, identifying an exception condition in response to elapse of a second time period without receipt by the repository of the second result, wherein the second time period begins when the first result is received by the repository; and

comparing the first and second results for consistency and controlling further execution of the first implementation and the second implementation in response to a result of the comparison.