Add-on memory coherence directory
First Claim
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1. An apparatus comprising:
- a processing chip in a multiprocessing data processing system;
wherein the processing chip comprises a plurality of processors;
wherein each processor within the plurality of processors comprises a processing core and a cache; and
wherein a given processor in the processing chip is configured to;
responsive to determining a number of sharers of a given memory region is greater than one and less than a threshold, mark the memory region as directory-based in an effective-to-real address translation table and storing a new directory entry for the memory re ion in an add-on cache directory;
responsive to a memory access resulting in a cache miss in the given processor, determine whether the accessed memory region is marked as directory-based in the effective-to-real address translation table;
responsive to the given processor determining the accessed memory region is not marked as directory-based, perform the memory access using a snooping protocol; and
responsive to the given processor determining the accessed memory region is marked as directory-based in the effective-to-real address translation table, access a directory entry corresponding to the accessed memory region from the add-on cache directory to identify a home chip for the accessed memory region using a directory-based protocol and forward the memory access request from the given processor to the home chip to perform the memory access.
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Abstract
A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory access resulting in a cache miss in a given processor, the processor determines whether a memory region being accessed is marked as directory-based. Responsive to the given processor determining the memory region is marked as directory-based, the given processor accesses a directory entry corresponding to the memory region to identify a home chip for the page using a directory-based protocol. The given processor forwards the memory access request to the home chip to perform the memory access.
59 Citations
19 Claims
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1. An apparatus comprising:
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a processing chip in a multiprocessing data processing system; wherein the processing chip comprises a plurality of processors; wherein each processor within the plurality of processors comprises a processing core and a cache; and wherein a given processor in the processing chip is configured to; responsive to determining a number of sharers of a given memory region is greater than one and less than a threshold, mark the memory region as directory-based in an effective-to-real address translation table and storing a new directory entry for the memory re ion in an add-on cache directory; responsive to a memory access resulting in a cache miss in the given processor, determine whether the accessed memory region is marked as directory-based in the effective-to-real address translation table; responsive to the given processor determining the accessed memory region is not marked as directory-based, perform the memory access using a snooping protocol; and responsive to the given processor determining the accessed memory region is marked as directory-based in the effective-to-real address translation table, access a directory entry corresponding to the accessed memory region from the add-on cache directory to identify a home chip for the accessed memory region using a directory-based protocol and forward the memory access request from the given processor to the home chip to perform the memory access. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the computing device to:
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responsive to determining a number of sharers of a given memory region is greater than one and less than a threshold, mark the memory region as directory-based in an effective-to-real address translation table and storing a new directory entry for the memory region in an add-on cache directory; responsive to a memory access resulting in a cache miss in a given processor, determine whether the accessed memory region is marked as directory-based in the effective-to-real address translation table; responsive to the given processor determining the accessed memory region is not marked as directory-based, perform the memory access using a snooping protocol; and responsive to the given processor determining the accessed memory region is marked as directory-based in the effective-to-real address translation table, access a directory entry corresponding to the accessed memory region from the add-on cache directory to identify a home chip far the accessed memory region using a directory-based protocol and forward the memory access request from the given processor to the home chip to perform the memory access. - View Dependent Claims (16, 17, 18, 19)
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Specification