Managing aliasing in a virtually indexed physically tagged cache

• US 9,842,051 B1
• Filed: 03/18/2016
• Issued: 12/12/2017
• Est. Priority Date: 03/25/2015
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Schuttenberg, Kim, Bryant, Richard, Jamil, Sujat, O'Bleness, R. Frank
• Primary Examiner(s): Elmore, Stephen
• Application Number:
  US15/074,764
• Time in Patent Office: 634 Days
• Field of Search: 711146, 711128, 711141, 711144, 711154, 711156, 711202
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/1063 the data cache being concurrently virtually addressed
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A circuit includes a Virtually Indexed Physically Tagged (VIPT) cache and a cache coherency circuit. The VIPT cache includes a plurality of sets and performs a memory operation by selecting, using a Virtual Set Address (VSA), a first tag of a first set. The cache coherency circuit is to detect cache aliasing during memory operations of the VIPT cache when a second tag maps a physical address to a second set of the VIPT cache, the second set being different than the first set. A method of managing a VIPT cache includes performing, by the VIPT cache, a memory operation and determining, using a cache coherency protocol, that cache aliasing has occurred during the memory operation.

Claims

1. A circuit comprising:

a Virtually Indexed Physically Tagged (VIPT) cache including a plurality of sets, the VIPT cache to perform a memory operation by (i) selecting, using a Virtual Set Address (VSA), a first tag of a first set of the VIPT cache, and (ii) determining whether the first tag maps a physical address to the first set by comparing a plurality of bits of the first tag to a plurality of bits of the physical address; and

a cache coherency circuit to detect cache aliasing during the performance of the memory operation by the VIPT cache,

wherein cache aliasing is detected when a second tag maps the physical address to a second set of the VIPT cache, the second set being different from the first set.

2. The circuit of claim 1, wherein the cache coherency circuit comprises:

first set coherency information corresponding to the first set that the physical address may be mapped into in the VIPT cache; and

second set coherency information corresponding to the second set that the physical address may be mapped into in the VIPT cache.

3. The circuit of claim 2, wherein the cache coherency circuit comprises a snoop filter to cache, according to the physical address, the first set coherency information and the second set coherency information.

4. The circuit of claim 3, wherein the snoop filter comprises a plurality of snoop filter entries, each snoop filter entry including an address tag and a plurality of set coherency information corresponding to a plurality of set address.

5. The circuit of claim 2, wherein the cache coherency circuit is to manage the first set coherency information and the second set coherency information according to a cache coherency protocol.

6. The circuit of claim 5, wherein the cache coherency protocol is one of a Modified-Exclusive-Shared-Invalid (MESI) coherence protocol, a Modified-Shared-Invalid (MSI) coherence protocol, a Modified-Owned-Shared-Invalid (MOSI) coherence protocol, and a Modified-Owned-Exclusive-Shared-Invalid (MOESI).

7. The circuit of claim 5, wherein the cache coherency circuit is to manage cache coherency between the VIPT cache and another cache according to the cache coherency protocol.

8. The circuit of claim 2, wherein the cache coherency circuit is to generate a snoop set address according to set coherency information of a snoop filter entry having an address tag corresponding to the physical address;

wherein the circuit is to access the VIPT cache using the VSA when cache aliasing is not detected; and

wherein the circuit access is to access the VIPT cache using the snoop set address when cache aliasing is detected.

9. The circuit of claim 8, wherein the VSA is generated according to a Virtual Address (VA), and the physical address is generated according to the VA.

10. The circuit of claim 9, wherein the VSA includes a first plurality of bits produced by an address translation of the VA, and a second plurality of bits equal to a plurality of bits of the VA that are not altered by the address translation of the VA.

11. A method for managing a Virtually Indexed Physically Tagged (VIPT) cache, the method comprising:

performing, by the VIPT cache, a memory operation, performing the memory operation including (i) selecting, by the VIPT cache using a Virtual Set Address (VSA), a first tag of a first set of the VIPT cache, and (ii) determining whether the first tag maps a Physical Address (PA) to the first set by comparing a plurality of bits of the first tag to a plurality of bits of the Physical Address;

determining, using a cache coherency protocol, that cache aliasing has occurred during the memory operation when a second tag maps the PA to a second set, the second set being different from the first set.

12. The method of claim 11, wherein determining that cache aliasing has occurred includes:

receiving the VSA, the VSA corresponding to a Virtual Address (VA);

receiving the PA, the PA corresponding to the VA;

selecting, using the VSA, respective cache lines from each of a plurality of ways of the VIPT cache;

determining, for each selected cache line respectively, whether an address tag of the selected cache line is valid and matches the PA; and

determining, using a cache coherency protocol, that a first cache line corresponding to the PA is present in the VIPT cache when none of the cache lines selected using the VSA have a valid address tag that matches the PA.

13. The method of claim 12, wherein determining, using the cache coherency protocol, whether the first cache line corresponding to the PA is present in the VIPT cache is performed using a snoop filter, the snoop filter caching, according to the physical address, first coherency information corresponding to the first set and second coherency information corresponding to the second set.

14. The method of claim 13, further comprising:

determining, using the snoop filter, a set address of the first cache line.

15. The method of claim 14, further comprising:

determining a second cache line corresponding to the VSA; and

copying information cached in the first cache line to the second cache line.

16. The method of claim 15, further comprising setting coherency information corresponding to the VSA to a modified state when the memory operation includes a write operation.

17. The method of claim 14, further comprising setting coherency information corresponding to the set address of the first cache line to an invalid state when the memory operation includes a write operation.

18. The method of claim 13, further comprising maintaining, using the snoop filter, cache coherency between the VIPT cache and another cache.

19. The method of claim 11, wherein the cache coherency protocol includes a modified state, a shared state, and an invalid state.

20. The method of claim 19, wherein the cache coherency protocol further includes one or more of an exclusive state and an owned state.