×

Address translation cache that supports simultaneous invalidation of common context entries

  • US 9,842,055 B2
  • Filed: 11/26/2014
  • Issued: 12/12/2017
  • Est. Priority Date: 07/21/2014
  • Status: Active Grant
First Claim
Patent Images

1. A translation-lookaside buffer (TLB), comprising:

  • a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a valid bit vector, wherein each bit of the valid bit vector indicates, for a respective address translation context, the address translation is valid if set and invalid if clear; and

    an invalidation bit vector having bits corresponding to the bits of the valid bit vector of the plurality of entries, wherein a set bit of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the valid bit vector of each entry of the plurality of entries.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×