Address translation cache that supports simultaneous invalidation of common context entries

• US 9,842,055 B2
• Filed: 11/26/2014
• Issued: 12/12/2017
• Est. Priority Date: 07/21/2014
• Status: Active Grant

• Current Assignee: Via Alliance Semiconductor Co., Ltd.
• Original Assignee: Via Alliance Semiconductor Co., Ltd.
• Inventors: Eddy, Colin, Mohan, Viswanath
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): Edouard, Jean
• Application Number:
  US14/890,334
• Publication Number:
  US 20160179701A1
• Time in Patent Office: 1,112 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 12/1063 the data cache being concurrently virtually addressed
• CPC Class Codes: G06F 12/109 for multiple virtual address spaces, e.g. segmentation G06F12/1036 takes precedence
• CPC Class Codes: G06F 15/7839 with memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/683 Invalidation
• CPC Class Codes: G06F 2212/684 TLB miss handling

Abstract

A processor includes a mapping module that maps architectural virtual processor identifiers to non-architectural global identifiers and maps architectural process context identifiers to non-architectural local identifiers. The processor also includes a translation-lookaside buffer (TLB) having a plurality of address translations. For each address translation of the plurality of address translations: when the address translation is a global address translation, the address translation is tagged with a representation of one of the non-architectural global identifiers to which the mapping module has mapped one of the virtual processor identifiers; and when the address translation is a local address translation, the address translation is tagged with a representation of one of the non-architectural local identifiers to which the mapping module has mapped one of the process context identifiers.

Claims

1. A translation-lookaside buffer (TLB), comprising:

a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a valid bit vector, wherein each bit of the valid bit vector indicates, for a respective address translation context, the address translation is valid if set and invalid if clear; and

an invalidation bit vector having bits corresponding to the bits of the valid bit vector of the plurality of entries, wherein a set bit of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the valid bit vector of each entry of the plurality of entries.

2. The TLB of claim 1, wherein the valid bit vector comprises global and local portions and the invalidation bit vector comprises global and local portions corresponding to the global and local portions of the valid bit vector, respectively, wherein the global and local portions are mutually exclusive, wherein the address translation is a valid local address translation when one or more bits of the local portion of the valid bit vector is set, wherein the address translation is a valid global address translation when one or more bits of the global portion of the valid bit vector is set.

3. The TLB of claim 2, wherein a set bit of the local portion of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the local portion of the valid bit vector of each entry of the plurality of entries and a set bit of the global portion of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the global portion of the valid bit vector of each entry of the plurality of entries.

4. The TLB of claim 3, wherein the TLB is configured to simultaneously clear the corresponding bit of the local portion of the valid bit vector of each entry of the plurality of entries and the corresponding bit of the global portion of the valid bit vector of each entry of the plurality of entries.

5. The TLB of claim 2,

wherein the address translation comprises a pair of memory addresses in which a first of the pair is an address to be translated and the second of the pair is a translated address;

wherein the TLB indicates a hit and provides the translated address of an entry of the plurality of entries whose address to be translated matches a lookup address provided to the TLB and whose local portion of the valid bit vector includes a set bit that matches a corresponding set bit of a lookup local bit vector provided to the TLB or whose global portion of the valid bit vector includes a set bit that matches a corresponding set bit of a lookup global bit vector provided to the TLB, and otherwise indicates a miss; and

wherein the lookup local bit vector and the lookup global bit vector collectively indicate a current address translation context associated with a process that generates the lookup address.

6. The TLB of claim 1,

wherein the address translation comprises a pair of memory addresses in which a first of the pair is an address to be translated and the second of the pair is a translated address;

wherein the TLB indicates a hit and provides the translated address of an entry of the plurality of entries whose address to be translated matches a lookup address provided to the TLB and whose valid bit vector includes a set bit that matches a corresponding set bit of a lookup bit vector provided to the TLB, and otherwise indicates a miss; and

wherein the lookup bit vector indicates a current address translation context associated with a process that generates the lookup address.

7. A method for operating a translation-lookaside buffer (TLB) comprising a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a valid bit vector, wherein each bit of the valid bit vector indicates, for a respective address translation context, the address translation is valid if set and invalid if clear, the method comprising:

receiving an invalidation bit vector having bits corresponding to the bits of the valid bit vector of the plurality of entries; and

simultaneously clearing the bit of the valid bit vector of each entry of the plurality of entries corresponding to a set bit of the invalidation bit vector.

8. The method of claim 7, wherein the valid bit vector comprises global and local portions and the invalidation bit vector comprises global and local portions corresponding to the global and local portions of the valid bit vector, respectively, wherein the global and local portions are mutually exclusive, wherein the address translation is a valid local address translation when one or more bits of the local portion of the valid bit vector is set, wherein the address translation is a valid global address translation when one or more bits of the global portion of the valid bit vector is set.

9. The method of claim 8, wherein said simultaneously clearing the bit of the valid bit vector of each entry of the plurality of entries corresponding to a set bit of the invalidation bit vector comprises:

simultaneously clearing the bit of the local portion of the valid bit vector of each entry of the plurality of entries corresponding to a set bit of the local portion of the invalidation bit vector; and

simultaneously clearing the bit of the global portion of the valid bit vector of each entry of the plurality of entries corresponding to a set bit of the global portion of the invalidation bit vector.

10. The method of claim 9, wherein said simultaneously clearing the bit of the local portion and said simultaneously clearing the bit of the global portion are performed simultaneously.

11. The method of claim 8, wherein the address translation comprises a pair of memory addresses in which a first of the pair is an address to be translated and the second of the pair is a translated address, wherein the method further comprises:

indicating a hit and providing the translated address of an entry of the plurality of entries whose address to be translated matches a lookup address provided to the TLB and whose local portion of the valid bit vector includes a set bit that matches a corresponding set bit of a lookup local bit vector provided to the TLB or whose global portion of the valid bit vector includes a set bit that matches a corresponding set bit of a lookup global bit vector provided to the TLB; and

otherwise indicating a miss; and

wherein the lookup local bit vector and the lookup global bit vector collectively indicate a current address translation context associated with a process that generates the lookup address.

12. The method of claim 7, wherein the address translation comprises a pair of memory addresses in which a first of the pair is an address to be translated and the second of the pair is a translated address, the method further comprising:

indicating a hit and providing the translated address of an entry of the plurality of entries whose address to be translated matches a lookup address provided to the TLB and whose valid bit vector includes a set bit that matches a corresponding set bit of a lookup bit vector provided to the TLB; and

otherwise indicating a miss; and

wherein the lookup bit vector indicates a current address translation context associated with a process that generates the lookup address.

13. The method of claim 7, further comprising:

generating a new address translation using a current address translation context in response to a miss in the TLB of a lookup address;

populating the address translation of one of the entries of the plurality of entries with the new address translation; and

populating the valid bit vector of the one of the entries of the plurality of entries with a bit-vectorized representation of a current context identifier that identifies a current address translation context associated with a process that generates the lookup address.

14. A processor, comprising:

translation-lookaside buffer (TLB), comprising;

a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a valid bit vector, wherein each bit of the valid bit vector indicates, for a respective address translation context, the address translation is valid if set and invalid if clear; and

an invalidation bit vector having bits corresponding to the bits of the valid bit vector of the plurality of entries, wherein a set bit of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the valid bit vector of each entry of the plurality of entries; and

a mapping module, configured to generate the invalidation bit vector.

15. The processor of claim 14, wherein the valid bit vector comprises global and local portions and the invalidation bit vector comprises global and local portions corresponding to the global and local portions of the valid bit vector, respectively, wherein the global and local portions are mutually exclusive, wherein the address translation is a valid local address translation when one or more bits of the local portion of the valid bit vector is set, wherein the address translation is a valid global address translation when one or more bits of the global portion of the valid bit vector is set.

16. The processor of claim 15, wherein a set bit of the local portion of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the local portion of the valid bit vector of each entry of the plurality of entries and a set bit of the global portion of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the global portion of the valid bit vector of each entry of the plurality of entries.

17. The processor of claim 16, wherein the TLB is configured to simultaneously clear the corresponding bit of the local portion of the valid bit vector of each entry of the plurality of entries and the corresponding bit of the global portion of the valid bit vector of each entry of the plurality of entries.

18. The processor of claim 15,

wherein the address translation comprises a pair of memory addresses in which a first of the pair is an address to be translated and the second of the pair is a translated address;

wherein the TLB indicates a hit and provides the translated address of an entry of the plurality of entries whose address to be translated matches a lookup address provided to the TLB and whose local portion of the valid bit vector includes a set bit that matches a corresponding set bit of a lookup local bit vector provided to the TLB or whose global portion of the valid bit vector includes a set bit that matches a corresponding set bit of a lookup global bit vector provided to the TLB, and otherwise indicates a miss; and

wherein the lookup local bit vector and the lookup global bit vector collectively indicate a current address translation context associated with a process that generates the lookup address.

19. The processor of claim 14,

wherein the address translation comprises a pair of memory addresses in which a first of the pair is an address to be translated and the second of the pair is a translated address;

wherein the TLB indicates a hit and provides the translated address of an entry of the plurality of entries whose address to be translated matches a lookup address provided to the TLB and whose valid bit vector includes a set bit that matches a corresponding set bit of a lookup bit vector provided to the TLB, and otherwise indicates a miss; and

wherein the lookup bit vector indicates a current address translation context associated with a process that generates the lookup address.

20. The processor of claim 14, further comprising:

a memory subsystem that generates a new address translation using a current address translation context in response to a miss in the TLB of a lookup address and populates the address translation of one of the entries of the plurality of entries with the new address translation and populates the valid bit vector of the one of the entries of the plurality of entries with a bit-vectorized representation of a current context identifier that identifies a current address translation context associated with a process that generates the lookup address.