Wear leveling in storage devices

• US 9,842,059 B2
• Filed: 04/14/2016
• Issued: 12/12/2017
• Est. Priority Date: 04/14/2016
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Kamruzzaman, Md
• Primary Examiner(s): Padmanabhan, Mano
• Assistant Examiner(s): EDOUARD, JEAN C
• Application Number:
  US15/098,668
• Publication Number:
  US 20170300423A1
• Time in Patent Office: 607 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 12/109 for multiple virtual address spaces, e.g. segmentation G06F12/1036 takes precedence
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/656 Address space sharing
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system may include a plurality of memory cells and a processor. The plurality of memory cells may include a plurality of physical locations at which data is stored. The processor may be configured to determine whether to swap physical locations of data stored at logical block addresses in the first logical block address collection and physical locations of data stored at logical block addresses in the second logical block address collection. The processor may be further configured to, in response to determining to swap the physical locations of the data, swap the physical locations of the data stored at the logical block addresses in the first logical block address collection and the physical locations of the data stored at the logical block addresses in the second logical block address collection.

Claims

1. A system comprising:

a plurality of memory devices comprising a plurality of physical locations at which data is stored;

a processor configured to;

determine, based on a value of a first transient write counter associated with a first logical block address collection and a value of a second transient write counter associated with a second logical block address collection, whether to swap physical locations of data stored at logical block addresses in the first logical block address collection and physical locations of data stored at logical block addresses in the second logical block address collection, wherein;

the value of the first transient write counter equals a number of times data has been written to the first logical block address collection since a prior data swap involving the first logical block address collection, and the value of the second transient write counter equals a number of times data has been written to the second logical block address collection since a prior data swap involving the second logical block address collection; and

in response to determining to swap the physical locations of the data stored at logical block addresses in the first logical block address collection and the physical locations of the data stored at logical block addresses in the second logical block address collection;

swap the physical locations of the data stored at the logical block addresses in the first logical block address collection and the physical locations of the data stored at the logical block addresses in the second logical block address collection; and

wherein the processor is configured to determine whether to swap physical locations of the data stored at logical block addresses in the first logical block address collection and physical locations of the data stored at logical block addresses in the second logical block address collection by at least;

summing the value of the first transient write counter with a value of a first permanent write counter associated with the first logical block address collection to determine a first total write value indicating a total number of writes to the first logical block address collection, wherein the value of the first permanent write counter equals the number of times data was written to the first logical block address collection before a prior data swap involving the first logical block address collection;

summing the value of the second transient write counter with a value of a second permanent write counter associated with the second logical block address collection to determine a second total write value indicating a total number of writes to the second logical block address collection, wherein the value of the second permanent write counter equals the number of times data was written to the second logical block address collection before a prior data swap involving the second logical block address collection; and

determining whether the first total write value is greater than a predetermined number multiplied by the second total write value.

2. The system of claim 1, wherein the processor is configured to determine whether to swap physical locations of the data stored at logical block addresses in the first logical block address collection and physical locations of the data stored at logical block addresses in the second logical block address collection by at least:

determine whether the value of the first transient write counter is greater than a predetermined number multiplied by the value of the second transient write counter.

3. The system of claim 1, wherein the processor is further configured to:

in response to determining that a sum of the value of the first transient write counter and a value of a first permanent write counter associated with the first logical block address collection exceeds a threshold block collection write count, rearrange, based on an offset value associated with the first logical block address collection, physical locations of data stored at logical addresses associated with the first logical block address collection; and

update the offset value associated with at least the first logical block address collection.

4. The system of claim 1, wherein, the processor is further configured to, in response to determining to swap physical locations of the data stored at logical block address in the first logical block address collection and physical locations of the data stored at logical block addresses in the second logical block address collection:

increase a value of a first permanent write counter associated with the first logical block address collection by the value of the first transient write counter; and

increase a value of a second permanent write counter associated with the second block collection by the value of the second transient write counter.

5. The system of claim 1, further comprising:

a data storage device comprising;

the plurality of memory devices; and

the processor.

6. The system of claim 1, further comprising:

a data storage device comprising the plurality of memory devices; and

a host device comprising the processor.

7. The system of claim 1, wherein the processor is further configured to:

in further response to determining to swap the physical locations of the data stored at logical block addresses in the first logical block address collection and the physical locations of the data stored at logical block addresses in the second logical block address collection;

set the value of the first transient counter and the value of the second transient write counter equal to a baseline value.

8. A method comprising:

determining, by a processor, based on a value of a first transient write counter associated with a first logical block address collection and a value of a second transient write counter second logical block address collection associated, whether to swap physical locations of data stored in the first logical block address collection and physical locations of data stored in the second logical block address collection, wherein;

the value of the first transient write counter equals a number of times data has been written to the first logical block address collection since a prior data swap involving the first logical block address collection, and the value of the second transient write counter equals a number of times data has been written to the second logical block address collection since a prior data swap involving the second logical block address collections and in response to determining to swap the physical locations of the data stored at logical block addresses in the first logical block address collection and the physical locations of the data stored at logical block addresses in the second logical block address collection;

causing, by the processor, the physical locations of the data stored at the logical block addresses in the first logical block address collection to be swapped with the physical locations of the data stored at the logical block addresses in the second logical block address collection; and

wherein determining whether to swap physical locations of the data stored at logical block addresses in the first logical block address collection and physical locations of the data stored at logical block addresses in the second logical block address collection comprises;

summing, by the processor, the value of the first transient write counter with a value of a first permanent write counter associated with the first logical block address collection to determine a first total write value indicating a total number of writes to the first logical block address collection, wherein the value of the first permanent write counter equals the number of times data was written to the first logical block address collection before a prior data swap involving the first logical block address collection;

summing, by the processor, the value of the second transient write counter with a value of a second permanent write counter associated with the second logical block address collection to determine a second total write value indicating a total number of writes to the second logical block address collection, wherein the value of the second permanent write counter equals the number of times data was written to the second logical block address collection before a prior data swap involving the second logical block address collection; and

determining, by the processor, whether the first total write value is greater than a predetermined number multiplied by the second total write value.

9. The method of claim 8, wherein determining whether to swap physical locations of the data stored at logical block addresses in the first logical block address collection and physical locations of the data stored at logical block addresses in the second logical block address collection comprises:

determining, by the processor, whether the value of the first transient write counter is greater than a predetermined number multiplied by the value of the second transient write counter.

10. The method of claim 8, further comprising:

in response to determining that a sum of the value of the first transient write counter and a value of a first permanent write counter associate with the first logical block address collection exceeds a threshold block collection write count, rearranging, by the processor and based on an offset value associated with the first logical block address collection, physical locations of data stored at logical addresses associated with the first logical block address collection; and

updating, by the processor, the offset value associated with at least the first logical block address collection.

11. The method of claim 8, further comprising:

in response to determining to swap physical locations of the data stored at logical block address in the first logical block address collection and physical locations of the data stored at logical block addresses in the second logical block address collection;

increasing, by the processor, a value of a first permanent write counter associated with the first logical block address collection by the value of the first transient write counter; and

increasing, by the processor, a value of a second permanent write counter associated with the second block collection by the value of the second transient write counter.

12. The method of claim 8, wherein determining whether to swap the physical locations of the data stored at logical block addresses in the first logical block address collection and the physical locations of data stored at logical block addresses in the second logical block address collection is in response to determining, by the processor, that a value of a device write counter satisfies a threshold device write count.

13. The method of claim 8, further comprising:

in further response to determining to swap the physical locations of the data stored at logical block addresses in the first logical block address collection and the physical locations of the data stored at logical block addresses in the second logical block address collection;

setting, by the processor, the value of the first transient counter and the value of the second transient write counter equal to a baseline value.