Processor communications

• US 9,842,067 B2
• Filed: 11/24/2015
• Issued: 12/12/2017
• Est. Priority Date: 12/12/2011
• Status: Active Grant

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Smith, David
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Hassan, Aurangzeb
• Application Number:
  US14/951,023
• Publication Number:
  US 20160077983A1
• Time in Patent Office: 749 Days
• Field of Search: None
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/423 with synchronous protocol
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence

Abstract

A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal.

Claims

1. An electronic device comprising:

a first processor configured to share data with a second processor; and

a first memory mapped peripheral associated with the first processor and configured to communicate with a second memory mapped peripheral associated with the second processor to control the sharing of the data, the first memory mapped peripheral comprising

a data acknowledgement generator configured to output a data acknowledgement signal to the second processor dependent on a data acknowledgement register write signal from the first processor, and

a data request waiting signal generator configured to output a data request waiting signal to the first processor dependent on a data request signal from the second processor, and the data acknowledgement signal, wherein the data acknowledgement generator comprises a toggle flip flop configured to receive as an input the data acknowledgement register write signal from the first processor and to output the data acknowledgement signal to the second processor.

2. The electronic device of claim 1, wherein the data request waiting signal generator comprises an XOR logic combiner configured to

receive as a first input an output of the toggle flip-flop,

receive as a second input the data request signal from the second processor, and

output the data request waiting signal to the first processor.

3. The electronic device of claim 2, wherein the data request waiting signal generator further comprises a data request synchronizer configured to synchronize the data request signal from the second processor into a clock domain of the first processor.

4. The electronic device of claim 1, further comprising a memory;

and wherein the first processor is configured to share data with the second processor via the memory.

5. An electronic device comprising:

a first circuit configured to share data with a second circuit; and

a first memory mapped peripheral associated with the first circuit and configured to communicate with a second memory mapped peripheral associated with the second circuit to control the sharing of the data, the first memory mapped peripheral comprising

a data acknowledgement generator configured to output a data acknowledgement signal to the second circuit dependent on a data acknowledgement register write signal from the first circuit, and

a data request waiting signal generator configured to output a data request waiting signal to the first circuit dependent on a data request signal from the second circuit, and the data acknowledgement signal, wherein the data acknowledgement generator comprises a toggle flip flop configured to receive as an input the data acknowledgement register write signal from the first circuit and to output the data acknowledgement signal to the second circuit.

6. The electronic device of claim 5, wherein the data request waiting signal generator comprises an XOR logic combiner configured to

receive as a first input an output of the toggle flip-flop,

receive as a second input the data request signal from the second circuit, and

output the data request waiting signal to the first circuit.

7. The electronic device of claim 6, wherein the data request waiting signal generator further comprises a data request synchronizer configured to synchronize the data request signal from the second circuit into a clock domain of the first circuit.

8. The electronic device of claim 5, further comprising a memory;

and wherein the first circuit is configured to share data with the second circuit via the memory.

9. A method comprising:

sharing data between a first processor and a second processor; and

communicating with the second processor to control the sharing of the data, wherein communicating with the second processor comprises controlling receiving data comprising

outputting a data acknowledgement signal to the second processor dependent on a data acknowledgement register write signal from the first processor, and

outputting a data request waiting signal to the first processor dependent on a data request signal from the second processor and the data acknowledgement signal, wherein outputting a data acknowledgement signal comprises configuring a toggle flip flop to receive as an input the data acknowledgement register write signal from the first processor and to output the data acknowledgement signal to the second processor.

10. The method as claimed in claim 9, wherein outputting a data request waiting signal comprises configuring an XOR logic combiner to

receive as a first input an output of the toggle flip-flop,

receive as a second input the data request signal from the second processor, and

output the data request waiting signal to the first processor.

11. The method as claimed in claim 10, wherein outputting a data request waiting signal further comprises synchronizing the data request signal from the second processor into a clock domain of the first processor.

12. The method as claimed in claim 9, wherein sharing data between the first processor and the second processor comprises sharing data via a memory.