Method and structure for enabling high aspect ratio sacrificial gates

• US 9,842,739 B2
• Filed: 04/18/2016
• Issued: 12/12/2017
• Est. Priority Date: 06/18/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Jung, Ryan O., Lie, Fee Li, Shearer, Jeffrey C., Sporre, John R., Teehan, Sean
• Primary Examiner(s): NGUYEN, SOPHIA T
• Application Number:
  US15/131,688
• Publication Number:
  US 20160233095A1
• Time in Patent Office: 603 Days
• CPC Class Codes: H01L 21/28132 conducting part of electrode is difined by a sidewall spacer or a similar technique, e.g. oxidation under mask, plating
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure.

Claims

1. A method of forming a semiconductor structure comprising:

forming a sacrificial gate stack comprising a sacrificial gate material layer and a sacrificial gate cap layer over a surface of a substrate;

providing a plurality of hard mask structures on a topmost surface of said sacrificial gate stack;

forming an anchoring element disposed over segments of each hard mask structure;

patterning said sacrificial gate stack into a plurality of sacrificial gate structures utilizing said plurality of hard mask structures and said anchoring element as an etch mask, wherein each sacrificial gate structure comprises a sacrificial gate material portion and a sacrificial gate cap portion, and wherein a pair of spaced apart sacrificial gate cap anchoring portions are present in which a first sacrificial gate cap anchoring portion contacts a first end segment of each of said sacrificial gate cap portions, and a second sacrificial gate cap anchoring portion contacts a second end segment of each of said sacrificial gate cap portions; and

removing each hard mask structure and said anchoring element to physically expose each sacrificial gate cap portion and each sacrificial gate cap anchoring portion.

2. The method of claim 1, further comprising forming a dielectric spacer comprising a first dielectric material on sidewalls of each sacrificial gate cap anchoring portion and on sidewalls of each sacrificial gate structure.

3. The method claim 2, further comprising forming a planarization dielectric layer laterally surrounding each of said sacrificial gate structures and in contact with a sidewall surface of the first dielectric spacer, wherein said planarization dielectric layer has a topmost surface that is coplanar with a topmost surface of each of said sacrificial gate structures.

4. The method of claim 1, wherein said forming said anchoring element comprises depositing a layer of a masking material, and patterning the layer of masking material by lithography and etching.

5. The method of claim 1, wherein said sacrificial gate stack further comprises a sacrificial gate dielectric material layer located beneath the sacrificial gate material layer.

6. The method of claim 1, wherein each of said sacrificial gate structure has a height from 50 nm to 200 nm, and a width from 5 nm to 30 nm.

7. The method of claim 1, wherein said sacrificial gate stack straddles a semiconductor fin that extends upward from a surface of said substrate.

8. The method of claim 1, wherein said anchoring element is formed orthogonal to each of said hard mask structures.

9. The method of claim 1, wherein said anchoring element has a height that is less than a height of each of said hard mask structures.

10. The method of claim 1, wherein said anchoring element has a height that is greater than a height of each of said hard mask structures.

11. The method of claim 1, wherein said anchoring element has a height that is equal to a height of each of said hard mask structures.

12. The method of claim 8, wherein said anchoring element has substantially vertical sidewalls.

13. The method of claim 8, wherein segments of each hard mask structure are end segments.

14. The method of claim 1, further comprising removing each sacrificial gate structure to provide gate cavities.

15. The method of claim 14, further comprising filling each gate cavity with a functional gate structure.

16. The method of claim 1, wherein each of sacrificial gate cap portion and each sacrificial gate cap anchoring portion are of unitary construction and are composed of a same gate cap material.