Integrated circuit device featuring an antifuse and method of making same

• US 9,842,802 B2
• Filed: 03/27/2014
• Issued: 12/12/2017
• Est. Priority Date: 06/29/2012
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Wang, Zhongze, Zhu, John Jianhong, Li, Xia
• Primary Examiner(s): Pizarro, Marcos D
• Assistant Examiner(s): GARCES, NELSON Y
• Application Number:
  US14/227,415
• Publication Number:
  US 20140210043A1
• Time in Patent Office: 1,356 Days
• Field of Search: 257525-535
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 28/24 with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• CPC Class Codes: H10B 20/60 Peripheral circuit regions

Abstract

One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first conductor plate, a dielectric layer, and a second conductor plate, where the dielectric layer is interposed between the first and second conductor plates. The antifuse transitions from an open circuit state to a closed circuit state if a programming voltage V_pp greater than or equal to a dielectric breakdown voltage V_BD of the antifuse is applied to the first conductor plate and the second conductor plate. The first conductor plate has a total edge length that is greater than two times the sum of its maximum width and maximum length dimensions. The first conductor plate'"'"'s top surface area may also be less than the product of its maximum length and maximum width.

Claims

1. An integrated circuit, comprising:

an antifuse having a conductor-insulator-conductor structure, the antifuse comprising

a top conductor plate,

a dielectric layer,

a bottom conductor plate, the dielectric layer interposed between the top and bottom conductor plates, and

at least one metal line comprising a surface irregularity, positioned under the bottom conductor plate, the surface irregularity being configured to cause weakness in at least the bottom conductor plate to lower a dielectric breakdown voltage V_BD of the antifuse,

wherein the antifuse configured to transition from an open circuit state to a closed circuit state if a programming voltage V_pp greater than or equal to the V_BD of the antifuse is applied to the top conductor plate and the bottom conductor plate, and

wherein the top conductor plate has a maximum width W_MAX and a maximum length L_MAX, and the top conductor plate has a total edge length L_TE according to an equation given by

L_TE>

2*(W_MAX+L_MAX).

2. The integrated circuit of claim 1, wherein the top conductor plate includes a first body portion having a first side, and a first plurality of fingers extending laterally from the first side of the first body portion, the first plurality of fingers each being rectangular and having a length L_F and positioned perpendicular lengthwise to the first side of the first body portion.

3. The integrated circuit of claim 2, wherein a number of the first plurality of fingers is equal to N, and the total edge length L_TE of the top conductor plate is given by an equation

L_TE=2*(W_WAX+L_MAX)+2*(N−

1)*L_F.

4. The integrated circuit of claim 2, wherein the top conductor plate further includes a second plurality of fingers extending laterally from a second side of the first body portion, the second side of the first body portion opposite the first side of the first body portion, the second plurality of fingers each being rectangular and having a length L_F and positioned perpendicular lengthwise to the second side of the first body portion.

5. The integrated circuit of claim 4, wherein a number of the first plurality of fingers is equal to a number of the second plurality of fingers and the total number of the first and second plurality of fingers is equal to N, and the total edge length L_TE of the top conductor plate is given by an equation

L_TE=2*(W_MAX+L_MAX)+2*(N−

2)*L_F.

6. The integrated circuit of claim 4, wherein a number of the first plurality of fingers is greater than a number of the second plurality of fingers and the total number of the first and second plurality of fingers is odd and equal to N, and the total edge length L_TE of the top conductor plate is given by an equation

L_TE=2*(W_MAX+L_MAX)+2*(N−

2)*L_F.

7. The integrated circuit of claim 2, wherein the top conductor plate further includes a second body portion having a second side, and the first plurality of fingers also extend laterally from the second side of the second body portion to couple the first and second body portions to each other.

8. The integrated circuit of claim 7, wherein a number of the first plurality of fingers is equal to N, the first plurality of fingers are spaced apart a distance W_S, and the total edge length L_TE of the top conductor plate is given by an equation

L_TE=2*(W_MAX+L_MAX)+2*(N−

1)*(L_F+W_S).

9. The integrated circuit of claim 2, wherein the top conductor plate further includes a second body portion having a second plurality of fingers, the first body portion not directly coupled to the second body portion.

10. The integrated circuit of claim 9, wherein the second body portion has a second side, and the second plurality of fingers extend laterally from the second side of the second body portion towards the first body portion, the second plurality of fingers each being rectangular and having a length L_F2 and positioned perpendicular lengthwise to the second side of the second body portion, and a distance between a distal edge of the second plurality of fingers and a first edge of the first body portion is L_S.

11. The integrated circuit of claim 10, wherein a number of the first plurality of fingers is one (1) less than a number of the second plurality of fingers and the total number of the first and second plurality of fingers is odd and equal to N, the distance L_S is equal to about half the length L_F and the length L_F2 (L_S=0.5*L_F=0.5*L_F2), and the total edge length L_TE of the top conductor plate is given by an equation

L_TE=2*(L_MAX+W_MAX)+(N−

2)*L_F+(N−

1)*L_F2+(N−

1)*W_F1+(N+1)*W_F2+2*(N−

1)*W_S,

wherein W_F1 represents a width of the first plurality of fingers, W_F2 represents a width of the second plurality of fingers, and W_S represents a space between the first plurality of fingers and the second plurality of fingers.

12. The integrated circuit of claim 1, wherein the at least one metal line is configured with an edge hump along its edges to cause a surface irregularity in at least a portion of the dielectric layer.

13. The integrated circuit of claim 1, wherein the at least one metal line comprises a plurality of metal lines oriented parallel to one another and having a length greater than at least one of the maximum length L_MAX and/or the maximum width W_MAX of the top conductor plate.

14. An integrated circuit, comprising:

an antifuse comprising

a top conductor plate,

a dielectric layer,

a bottom conductor plate, the dielectric layer interposed between the top and bottom conductor plates, and

a plurality of metal lines comprising surface irregularities positioned under the bottom conductor plate, the surface irregularities being configured to cause weakness in at least the bottom conductor plate to lower a dielectric breakdown voltage V_BD of the antifuse,

wherein the antifuse configured to transition from an open circuit state to a closed circuit state if a programming voltage V_pp greater than or equal to the V_BD of the antifuse is applied between the top conductor plate and the bottom conductor plate, and

wherein the top conductor plate has a maximum width W_MAX along a first axis, and a maximum length L_MAX along a second axis, the first axis and the second axis perpendicular to one another, and the top conductor plate has a total edge length L_TE according to an equation given by

L_TE>

2*(W_MAX+L_MAX),

and the top conductor plate has a top surface having an area S_TP that is less than W_MAX*L_MAX.

15. The integrated circuit of claim 14, wherein the top conductor plate is positioned above the bottom conductor plate, and wherein the plurality of metal lines are oriented parallel to one another and having a length greater than at least one of the maximum length L_MAX and/or the maximum width W_MAX of the top conductor plate.

16. The integrated circuit of claim 15, wherein at least one of the plurality of metal lines is configured with an edge hump along its edges to cause a surface irregularity in at least a portion of the dielectric layer.

17. The integrated circuit of claim 15, wherein the top conductor plate includes a first body portion having a first side, and a first plurality of fingers extending laterally from the first side of the first body portion.

18. The integrated circuit of claim 17, wherein the top conductor plate further includes a second plurality of fingers extending laterally from a second side of the first body portion, the second side of the first body portion opposite the first side of the first body portion.

19. The integrated circuit of claim 17, wherein the top conductor plate further includes a second body portion having a second side, and the first plurality of fingers also extend laterally from the second side of the second body portion to couple the first and second body portions to each other.

20. The integrated circuit of claim 17, wherein the top conductor plate further includes a second body portion having a second side, and a second plurality of fingers extend laterally from the second side of the second body portion towards the first body portion.