Butted body contact for SOI transistor

• US 9,842,858 B2
• Filed: 03/23/2016
• Issued: 12/12/2017
• Est. Priority Date: 11/18/2015
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Willard, Simon Edward
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US15/078,930
• Publication Number:
  US 20170141126A1
• Time in Patent Office: 629 Days
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/213 in integrated circuits
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence

Abstract

Systems, methods, and apparatus for an improved body tie construction are described. The improved body tie construction is configured to have a lower resistance body tie exists when the transistor is “off” (Vg approximately 0 volts). When the transistor is “on” (Vg>Vt), the resistance to the body tie is much higher, reducing the loss of performance associated with presence of body tie. Space efficient Body tie constructions adapted for cascode configurations are also described.

Claims

1. A semiconductor structure comprising a plurality of transistors, the semiconductor structure comprising:

an insulating layer;

a silicon layer overlying the insulating layer;

active regions formed in the silicon layer, the active regions extending through the silicon layer to contact the insulating layer, the active regions comprising body regions, source regions and drain regions of one or more fingers of each transistor of the plurality of transistors configured as a cascode stack arranged from top to bottom, wherein for each two consecutive transistors of the cascode stack, a source region of a finger of a top transistor and the drain region of a finger of a bottom transistor of the each two consecutive transistors are formed in a common source/drain region of the silicon layer; and

at least one butted body tie structure associated to the top finger, comprising;

i) a non-conductive isolation region;

ii) a body contact region formed within the common source/drain region of the fingers of two consecutive transistors separate from the body regions of the fingers and abutting an isolation region of the non-conductive isolation region; and

iii) a body tab region formed in the silicon layer in contact with the body region of the finger of the top transistor and the body contact region,

wherein the at least one non-conductive isolation region is configured to;

form an interruption in a region of the silicon layer which defines the body region of the finger of the bottom transistor to divide said body region in separate body regions, and

extend the interruption in a region of the silicon layer which defines body regions and common source/drain regions of fingers of one or more consecutive transistors adjacent to the bottom transistor to divide said regions in separate regions.

2. The semiconductor structure of claim 1, further comprising:

additional butted body tie structures associated to the bottom finger, wherein the body tab region of each of the additional butted body tie structures is in contact with a separate body region of the finger of the bottom transistor.

3. The semiconductor structure of claim 2, wherein:

each finger of a transistor of the plurality of transistors comprises a number of associated butted body tie structures equal to a number of separate body regions of the each finger, and

the body tab region of each of the associated butted body tie structures is in contact with a separate body region of the each finger.

4. The semiconductor structure of claim 1 or claim 2, wherein:

the cascode stack comprises a first top transistor and a last bottom transistor,

each transistor of the plurality of transistors of the cascode stack comprises two or more fingers; and

regions of any two fingers of the each transistor are mirrored around a centerline defined by a center region of a common source region along a width of the common source region, the common source region being the source region of two fingers of the last bottom transistor.

5. The semiconductor structure of claim 4, wherein the semiconductor structure is symmetric with respect to the centerline.

6. The semiconductor structure of claim 5, wherein the semiconductor structure is symmetric with respect to a centerline passing through centers of the one or more fingers of each transistor of the plurality of transistors along the length of the one or more fingers.

7. The semiconductor structure of claim 4, wherein each finger of the first top transistor comprises one and only one associated butted body tie structure.

8. The semiconductor structure of claim 7, wherein the semiconductor structure is symmetric with respect to a centerline passing through centers of the one or more fingers of each transistor of the plurality of transistors along the length of the one or more fingers.

9. The semiconductor structure of claim 4, wherein each finger of a transistor adjacent to the first top transistor comprises one and only one associated butted body tie structure.

10. The semiconductor structure of claim 9, wherein regions of any two fingers of the each transistor are further mirrored around a centerline defined by a center region of a common drain region along a width of the common drain region, the common drain region being the drain region of two fingers of the first top transistor, the two fingers comprising a first top finger and a second top finger, the semiconductor structure further comprising:

a perpendicular polysilicon structure joining gate polysilicon structures of the first and the second top fingers, the perpendicular polysilicon structure defining an underlying common body region to the body regions of the first and the second top fingers; and

a horizontal polysilicon structure extending from a midpoint of the perpendicular polysilicon structure through an edge of a silicon region of the semiconductor structure, the horizontal polysilicon structure extending the underlying common body region to the edge of the silicon region.

11. The semiconductor structure of claim 10, wherein the semiconductor structure is symmetric with respect to a centerline passing through centers of the one or more fingers of each transistor of the plurality of transistors along the length of the one or more fingers.