Insulated gate semiconductor device having a shield electrode structure and method

• US 9,842,925 B2
• Filed: 10/25/2016
• Issued: 12/12/2017
• Est. Priority Date: 07/21/2014
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Deng, Shengling, Hossain, Zia
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US15/333,441
• Publication Number:
  US 20170040447A1
• Time in Patent Office: 413 Days
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a semiconductor region with a charge balance region on a junction blocking region, the junction blocking region having a lower doping concentration. The junction blocking region extends between a pair of trench structures in cross-sectional view. The trench structures are provided in the semiconductor region and include at least one insulated electrode. In some embodiments, the semiconductor device further includes a first doped region disposed between the pair of trench structures. The semiconductor device may further include one or more features configured to improve operating performance. The features include a localized doped region adjoining a lower surface of a first doped region and spaced apart from the trench structure, a notch disposed proximate to the lower surface of the first doped region, and/or the at least one insulated electrode configured to have a wide portion adjoining a narrow portion.

Claims

1. A semiconductor device structure comprising:

a region of semiconductor material comprising;

a semiconductor substrate;

a first semiconductor layer of a first conductivity type and a first dopant concentration on the semiconductor substrate; and

a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having the first conductivity type, having a second dopant concentration greater than the first dopant concentration, and having a major surface;

a first trench structure in the first semiconductor layer and the second semiconductor layer extending from the major surface, and wherein the first trench structure comprises;

a first trench terminating within the first semiconductor layer; and

a first insulated electrode;

a second trench structure in the first semiconductor layer and the second semiconductor layer extending from the major surface and laterally spaced apart from the first trench structure, and wherein the second trench structure comprises;

a second trench terminating within the first semiconductor layer; and

a second insulated electrode;

a first conductive structure electrically coupled to the second semiconductor layer, wherein the second semiconductor layer is a continuous layer extending between the first trench and the second trench; and

a first doped region of the second conductivity type in the second semiconductor layer, wherein;

a portion of the second semiconductor layer separates the first doped region from the first trench structure,

another portion of the second semiconductor layer separates the first doped region from the second trench structure, and

a further portion of the second semiconductor layer separates the first doped region from the first semiconductor layer.

2. The semiconductor device of claim 1 further comprising a second doped region of a second conductivity type interposed between the first trench structure and the second trench structure, wherein the first conductive structure is electrically connected to the second doped region.

3. The semiconductor device of claim 2 wherein:

the first doped region is disposed adjacent a lower surface of the second doped region.

4. The semiconductor device of claim 2 further comprising:

a third insulated electrode disposed in the first trench structure and insulated from the first insulated electrode; and

a fourth insulated electrode disposed in the second trench structure and insulated from the second insulated electrode.

5. The semiconductor device structure of claim 4, wherein:

the first insulated electrode comprises a first gate electrode;

the second insulated electrode comprises a second gate electrode;

the third insulated electrode comprises a first insulated shield electrode below the first insulated gate electrode;

the fourth insulated electrode comprises a second insulated shield electrode below the second insulated gate electrode;

the second doped region comprises a body region; and

the semiconductor device further comprises;

a first source region of the first conductivity type in the body region adjacent the first trench structure; and

a second source region of the first conductivity type in the body region adjacent the second trench structure.

6. The semiconductor device structure of claim 5, wherein the first doped region adjoins the lower surface of the body region.

7. The semiconductor device structure of claim 5, wherein the first doped region is spaced apart from the body region.

8. The semiconductor device structure of claim 5 further comprising a third doped region of the first conductivity type in the second semiconductor layer adjacent the first doped region and adjacent the first and second trench structures.

9. The semiconductor device structure of claim 4, wherein the third insulated electrode comprises a first portion and a second portion, wherein the first portion is wider than the second portion.

10. The semiconductor device of claim 1 further comprising:

a third insulated electrode disposed in the first trench structure and insulated from the first insulated electrode; and

a fourth insulated electrode disposed in the second trench structure and insulated from the second insulated electrode.

11. The semiconductor device structure of claim 10, wherein the first trench structure comprises a sidewall profile having a notch oriented substantially inward towards an inner portion of the first trench and adjacent the second semiconductor layer.

12. A semiconductor device structure comprising:

a region of semiconductor material comprising;

a semiconductor substrate;

a first semiconductor layer of a first conductivity type and a first dopant concentration on the semiconductor substrate; and

a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having the first conductivity type, having a second dopant concentration greater than the first dopant concentration, and having a major surface;

a trench structure in the first semiconductor layer and the second semiconductor layer extending from the major surface, and wherein the trench structure comprises;

a first trench portion terminating within the first semiconductor layer;

a first insulated electrode disposed in the first trench portion;

a second insulated electrode disposed in the first trench portion and insulated from the first insulated electrode;

a second trench portion terminating within the first semiconductor layer and laterally spaced apart from the first trench portion;

a third insulated electrode disposed in the second trench portion; and

a fourth insulated electrode disposed in the second trench portion and insulated from the third insulated electrode, wherein;

the second semiconductor layer is a continuous layer extending between the first trench portion and the second trench portion; and

a first doped region of the second conductivity type disposed within the second semiconductor layer, wherein;

a portion of the second semiconductor layer separates the first doped region from the first trench portion, and

another portion of the second semiconductor layer separates the first doped region from the second trench portion.

13. The semiconductor device structure of claim 12 further comprising:

a first conductive structure electrically coupled to the second semiconductor layer; and

a second doped region of a second conductivity type disposed in the second semiconductor layer and interposed between the first trench portion and the second trench portion.

14. The semiconductor device structure of claim 13, wherein

the first doped region is disposed adjacent a lower surface of the second doped region.

15. The semiconductor device structure of claim 12, wherein the second dopant concentration is at least 500% greater than the first dopant concentration.

20. The semiconductor device structure of claim 13, wherein the first doped region is spaced apart from the second doped region.

16. A semiconductor device structure comprising:

a region of semiconductor material comprising;

a semiconductor substrate;

a first semiconductor layer of a first conductivity type and a first dopant profile on the semiconductor substrate; and

a second semiconductor layer on the first semiconductor layer, the second semiconductor layer having the first conductivity type, having a second dopant profile different than the first dopant profile, and having a major surface;

a first trench structure in the first semiconductor layer and the second semiconductor layer extending from the major surface, wherein the first trench structure comprises;

a first trench terminating within the first semiconductor layer; and

a first insulated electrode;

a second trench structure in the first semiconductor layer and the second semiconductor layer extending from the major surface and laterally spaced apart from the first trench structure, wherein the second trench structure comprises;

a second trench terminating within the first semiconductor layer; and

a second insulated electrode;

a first conductive layer electrically coupled to the second semiconductor layer, wherein the second semiconductor layer is a continuous layer extending between the first trench and the second trench; and

a first doped region of the second conductivity type disposed within the second semiconductor layer and spaced apart from a major surface of the second semiconductor layer, wherein;

a portion of the second semiconductor layer separates the first doped region from the first trench structure,

another portion of the second semiconductor layer separates the first doped region from the second trench structure, and

a further portion of the second semiconductor layer separates the first doped region from the first semiconductor layer.

17. The semiconductor device structure of claim 16 further comprising:

a second doped region of a second conductivity type interposed between the first trench structure and the second trench structure, wherein the first conductive layer is electrically connected to the second doped region;

a third insulated electrode disposed in the first trench structure and insulated from the first insulated electrode; and

a fourth insulated electrode disposed in the second trench structure and insulated from the second insulated electrode, wherein the second semiconductor layer has a dopant concentration that is at least 90% greater than that of the first semiconductor layer.

18. The semiconductor device structure of claim 17, wherein:

the first insulated electrode comprises a first gate electrode;

the second insulated electrode comprises a second gate electrode;

the third insulated electrode comprises a first insulated shield electrode below the first insulated gate electrode;

the fourth insulated electrode comprises a second insulated shield electrode below the second insulated gate electrode;

the second doped region comprises a body region; and

the semiconductor device further comprises;

a first source region of the first conductivity type in the body region adjacent the first trench structure; and

a second source region of the first conductivity type in the body region adjacent the second trench structure.

19. The semiconductor device structure of claim 17, further comprising:

a third doped region of the first conductivity type disposed within the second semiconductor layer adjacent the first and second trench structures, wherein at least portion of the first doped region is disposed within the third doped region.