Systems and methods for switched-inductor integrated voltage regulators

• US 9,843,262 B2
• Filed: 06/14/2016
• Issued: 12/12/2017
• Est. Priority Date: 08/26/2011
• Status: Active Grant

• Current Assignee: Trustees Of Columbia University In The City Of New York (Columbia University)
• Original Assignee: Trustees Of Columbia University In The City Of New York (Columbia University)
• Inventors: Shepard, Kenneth L., Sturcken, Noah Andrew
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US15/182,100
• Publication Number:
  US 20170110968A1
• Time in Patent Office: 546 Days
• Field of Search: 363268, 363272, 363282, 363283, 363285, 363351, 323268, 323272, 323282, 323283, 323285, 323351
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel

Abstract

Power controller includes an output terminal having an output voltage, at least one clock generator to generate a plurality of clock signals and a plurality of hardware phases. Each hardware phase is coupled to the at least one clock generator and the output terminal and includes a comparator. Each hardware phase is configured to receive a corresponding one of the plurality of clock signals and a reference voltage, combine the corresponding clock signal and the reference voltage to produce a reference input, generate a feedback voltage based on the output voltage, compare the reference input and the feedback voltage using the comparator and provide a comparator output to the output terminal, whereby the comparator output determines a duty cycle of the power controller. An integrated circuit including the power controller is also provided.

Claims

1. A power controller, comprising:

an output terminal having an output voltage;

at least one clock generator to generate a plurality of clock signals;

a plurality of hardware phases, each hardware phase being coupled to the at least one clock generator and the output terminal and including a comparator, each hardware phase being configured to;

receive a corresponding one of the plurality of clock signals and a reference voltage;

combine the corresponding clock signal and the reference voltage to produce a reference input;

generate a feedback voltage based on the output voltage;

compare the reference input and the feedback voltage using the comparator; and

provide a comparator output to the output terminal, whereby the comparator output determines a duty cycle of the power controller;

wherein the comparator comprises a zero voltage switching logic (ZVS);

wherein the comparator is configured to generate non-linear feedback gain.

2. The power controller of claim 1, wherein the plurality of hardware phases comprise four hardware phases.

3. The power controller of claim 1, wherein the plurality of hardware phases comprise unlatched hardware phases.

4. The power controller of claim 1, wherein each of the plurality of clock signals has a different phase.

5. The power controller of claim 1, wherein the reference input comprises a triangle wave potential.

6. The power controller of claim 5, wherein the triangle wave potential is centered at a desired DC output voltage of the power controller.

7. The power controller of claim 1, further comprising a bridge switching node having a bridge switching node voltage, the feedback voltage being further based on the bridge switching node voltage.

8. The power controller of claim 7, wherein the bridge switching node voltage is determined from an inductor current of the bridge switching node.

9. The power controller of claim 1, wherein the comparator is an unlatched continuous comparator.

10. An integrated circuit chip comprising the power controller of claim 1.

11. The integrated circuit chip of claim 10, further comprising one or more network-on-chip coupled to the power controller.

12. The integrated circuit chip of claim 11, wherein the one or more network- on-chip comprises four networks-on-chip, each network-on-chip having 64 cores.

13. A method comprising:

for each one of a plurality of hardware phases, each hardware phase being coupled to at least one clock generator and an output terminal and including a comparator;

receiving a corresponding one of a plurality of clock signals from the at least one clock generator and a reference voltage;

combining the corresponding clock signal and the reference voltage to produce a reference input;

generating a feedback voltage based on an output voltage from an output terminal;

comparing the reference input and the feedback voltage using the comparator;

providing a comparator output to the output terminal, whereby the comparator output determines a duty cycle of a power controller;

wherein the comparator comprises a zero voltage switching logic (ZVS);

wherein the comparator is configured to generate a non-linear feedback gain.

14. The method of claim 13, further comprising providing the plurality of clock signals, each of the plurality of clock signals having a different phase.

15. The method of claim 13, further comprising providing the reference input, wherein the reference input comprises a triangle wave potential.

16. The method of claim 15, wherein providing the reference input comprises centering the triangle wave potential at a desired DC output voltage of the power controller.

17. The method of claim 13, generating the feedback voltage further comprises generating the feedback voltage based on a bridge switching node voltage from a bridge switching node.

18. The method of claim 17, further comprising determining the bridge switching node voltage from an inductor current of the bridge switching node.