High di/dt capacity measurement hardware

• US 9,846,182 B2
• Filed: 05/30/2014
• Issued: 12/19/2017
• Est. Priority Date: 05/30/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Meng, Pon Tiam, Siew, Tai Chee
• Primary Examiner(s): Hollington, Jermele M
• Assistant Examiner(s): RAJAPUTRA, SURESH KS
• Application Number:
  US14/291,085
• Publication Number:
  US 20150346242A1
• Time in Patent Office: 1,299 Days
• CPC Class Codes: G01R 19/0092 measuring current only all subgroups of G01R19/00 take precedence
• CPC Class Codes: G01R 31/2608 for testing bipolar transistors
• CPC Class Codes: G01R 31/2621 for testing field effect transistors, i.e. FET's
• CPC Class Codes: G01R 31/2639 for testing field-effect devices, e.g. of MOS-capacitors G01R31/2621 takes precedence
• CPC Class Codes: G01R 31/40 Testing power supplies testing photovoltaic devices H02S50/10

Abstract

Hardware test systems are provided that have an electrical test loop with a minimum length of less than 200 mm, a maximum di/dt capacity of at least 1500 A/μs and a minimum parasitic inductance of less than 100 nH. The hardware tests systems can be used for commutation measurement or other test applications requiring low stray inductance.

Claims

1. A hardware test system, comprising:

a board comprising an insulating member and electrically conductive traces insulated from one another by the insulating member;

an energy storage system attached to the board, the energy storage system having first and second terminals at different polarities, the first terminal being connected to a first one of the traces and the second terminal being connected to a second one of the traces;

a control unit attached to the board and electrically connected to the first trace;

a DUT (device under test) input terminal attached to the same side of the board as the control unit and electrically connected to the control unit;

a DUT output terminal attached to the same side of the board as the control unit and electrically connected to the second trace; and

an electrical pathway from the first terminal to the second terminal of the energy storage system through the first trace, the control unit, the DUT and the second trace, the electrical pathway having a minimum length of less than 200 mm, a maximum di/dt capacity of at least 1500 A/μ

s and a minimum parasitic inductance of less than 100 nH.

2. The hardware test system of claim 1;

wherein the minimum length of the electrical pathway is 150 mm or less.

3. The hardware test system of claim 1, wherein the maximum di/dt capacity of the electrical pathway is 1900 A/μ

s or greater.

4. The hardware test system of claim 1, wherein the minimum parasitic inductance of the electrical pathway is 55 nH or less.

5. The hardware test system of claim 1, wherein the control unit is connected to a third one of the traces and wherein the first and the third traces each have an extension spaced apart from one another and extending outwardly in parallel with one another from the first and third traces.

6. The hardware test system of claim 5, further comprising an electrically conductive bridge connecting the first and the third traces at a region along the length of the extensions of the first and third traces.

7. The hardware test system of claim 6, wherein placement of the bridge along the length of the extensions of the first and third traces is adjustable to modify the length, maximum di/dt capacity and minimum parasitic inductance of the electrical pathway.

8. The hardware test system of claim 1, further comprising a current meter inductively coupled to the second trace between the DUT output terminal and the energy storage system, the current meter operable to measure current commutation of a DUT connected to the DUT input and output terminals at a di/dt of at least 1500 A/μ

s.

9. The hardware test system of claim 1, further comprising a temperature unit attached to the same side of the board as the control unit and operable to change the temperature of a DUT connected to the DUT input and output terminals.

10. A hardware test system, comprising:

a first board comprising a first electrically conductive sheet, an insulating sheet on the first electrically conductive sheet and a second electrically conductive sheet on the insulating sheet, the insulating sheet electrically insulating the first and second electrically conductive sheets from one another;

an energy storage system comprising one or more first cells disposed below the first electrically conductive sheet and one or more second cells disposed above the second electrically conductive sheet, each of the first cells having a first terminal connected to the first electrically conductive sheet and a second terminal connected to the second electrically conductive sheet, each of the second cells having a first terminal connected to the first electrically conductive sheet and a second terminal connected to the second electrically conductive sheet, the first terminals of the first and second cells being at a different polarity than the second terminals of the first and second cells;

a second board disposed on the second electrically conductive sheet and comprising;

a first terminal connected to the first electrically conductive sheet;

a second terminal connected to the second electrically conductive sheet;

a DUT (device under test) interface; and

a control unit operable to control operation of a DUT connected to the DUT interface; and

an electrical pathway from the first terminals of the first and second cells to the second terminals of the first and second cells through the first electrically conductive sheet, the control unit, the DUT and the second electrically conductive sheet, the electrical pathway having a minimum length of less than 100 mm, a maximum di/dt capacity of at least 2000 A/μ

s and a minimum parasitic inductance of less than 50 nH.

11. The hardware test system of claim 10, wherein the minimum length of the electrical pathway is 80 mm or less.

12. The hardware test system of claim 10, wherein the maximum di/dt capacity of the electrical pathway is 2800 A/μ

s or greater.

13. The hardware test system of claim 10, wherein the minimum parasitic inductance of the electrical pathway is 40 or less.

14. The hardware test system of claim 10, further comprising first and second extensions spaced apart from one another and extending outwardly in parallel with one another from the second electrically conductive sheet, and wherein the first terminal of the second board is connected to one of the first and second extensions of the second electrically conductive sheet and the other extension is connected to the second electrically conductive sheet.

15. The hardware test system of claim 14, further comprising an electrically conductive bridge connecting the first and second extensions at a region along the length of the first and second extensions.

16. The hardware test system of claim 15, wherein placement of the bridge along the length of the first and second extensions is adjustable to modify the length;

maximum di/dt capacity and minimum parasitic inductance of the electrical pathway.

17. The hardware test system of claim 10, further comprising a current meter inductively coupled to the first or the second electrically conductive sheet and operable to measure current commutation of the DUT connected to the DUT interface at a di/dt of at least 1500 A/μ

s.

18. The hardware test system of claim 10, wherein:

the first electrically conductive sheet has a plurality of openings, the insulating sheet has a first plurality of openings aligned over the openings in the first electrically conductive sheet and a second plurality of openings spaced apart from the first plurality of openings, and the second electrically conductive sheet has a plurality of openings aligned over the second plurality of openings in the insulating sheet;

the first terminals of the first cells are connected to a side of the first electrically conductive sheet facing the first cells;

the second terminals of the first cells are connected to the second electrically conductive sheet through the openings in the first electrically conductive sheet and the first plurality of openings in the insulating sheet;

the first terminals of the second cells are connected to the first electrically conductive sheet through the openings in the second electrically conductive sheet and the second plurality of openings in the insulating sheet; and

the second terminals of the second cells are connected to a side of the second electrically conductive sheet facing the second cells.

19. The hardware test system of claim 10, wherein the first and the second electrically conductive sheets are charged to opposite polarities by the energy storage system and aligned one above the other to cancel EM (electromagnetic) energy and reduce stray inductance.

20. The hardware test system of Maim 10, wherein the second board is centered between the first and second cells of the energy storage system.

21. A hardware test system comprising an electrical test loop having a minimum length of less than 200 mm, a maximum di/dt capacity of at least 1500 A/μ

s and a minimum parasitic inductance of less than 100 nH.