Method and apparatus for asynchronous processor pipeline and bypass passing
First Claim
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1. A clock-less asynchronous processor, comprising:
- a plurality of parallel asynchronous processing unit cores, each parallel asynchronous processing unit core configured to generate an instruction execution result;
an asynchronous instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the parallel asynchronous processing unit cores;
a register file coupled to each asynchronous processing unit core, the register file configured to store the instruction execution results and provide each of the plurality of parallel asynchronous processing unit cores direct access to the instruction execution results stored at the register file; and
a crossbar coupled to each asynchronous processing unit core, the crossbar configured to store the instruction execution results and to bypass the register file, wherein bypassing the register file provides each of the plurality of parallel asynchronous processing unit cores direct access to the instruction execution results stored at the crossbar.
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Abstract
A clock-less asynchronous processor comprising a plurality of parallel asynchronous processing logic circuits, each processing logic circuit configured to generate an instruction execution result. The processor comprises an asynchronous instruction dispatch unit coupled to each processing logic circuit, the instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the processing logic circuits. The processor comprises a crossbar coupled to an output of each processing logic circuit and to the dispatch unit, the crossbar configured to store the instruction execution results.
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Citations
18 Claims
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1. A clock-less asynchronous processor, comprising:
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a plurality of parallel asynchronous processing unit cores, each parallel asynchronous processing unit core configured to generate an instruction execution result; an asynchronous instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the parallel asynchronous processing unit cores; a register file coupled to each asynchronous processing unit core, the register file configured to store the instruction execution results and provide each of the plurality of parallel asynchronous processing unit cores direct access to the instruction execution results stored at the register file; and a crossbar coupled to each asynchronous processing unit core, the crossbar configured to store the instruction execution results and to bypass the register file, wherein bypassing the register file provides each of the plurality of parallel asynchronous processing unit cores direct access to the instruction execution results stored at the crossbar. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A clock-less asynchronous processor, comprising:
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a plurality of parallel asynchronous processing logic circuits, each parallel asynchronous processing logic circuit configured to generate an instruction execution result; an asynchronous instruction dispatch unit coupled to each parallel asynchronous processing logic circuit, the asynchronous instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the parallel asynchronous processing logic circuits; a register file coupled to each parallel asynchronous processing logic circuit, the register file configured to store the instruction execution results and provide each of the plurality of parallel asynchronous processing logic circuits direct access to the instruction execution results stored at the register file; and a crossbar coupled to each parallel asynchronous processing logic circuit and to the asynchronous instruction dispatch unit, the crossbar configured to store the instruction execution results and to bypass the register file, wherein bypassing the register file provides each of the plurality of parallel asynchronous processing logic circuits direct access to the instruction execution results stored at the crossbar. - View Dependent Claims (14)
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15. A method for operating an asynchronous processing system comprising a plurality of parallel asynchronous processing units, an asynchronous instruction dispatch unit coupled to each parallel asynchronous processing unit, a crossbar coupled to each parallel asynchronous processing unit and to the asynchronous instruction dispatch unit, and a register file coupled to each parallel asynchronous processing unit and to the asynchronous instruction dispatch unit, the method comprising:
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receiving multiple instructions from memory and dispatching individual instructions to each of the parallel asynchronous processing units; asynchronously processing a first instruction at a first parallel asynchronous processing unit of the parallel asynchronous processing units; storing a first execution result from the first parallel asynchronous processing unit in the crossbar; storing the first execution result from the first parallel asynchronous processing unit in the register file; and in response to the first execution result being currently stored in the crossbar, directly obtaining the first execution result from the crossbar and bypassing a fetch operation for direct access to the first execution result stored in the register file. - View Dependent Claims (16, 17, 18)
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Specification