Method and apparatus for asynchronous processor pipeline and bypass passing

• US 9,846,581 B2
• Filed: 09/08/2014
• Issued: 12/19/2017
• Est. Priority Date: 09/06/2013
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Huang, Tao, Ge, Yiqun, Zhang, Qifan, Shi, Wuxian, Tong, Wen
• Primary Examiner(s): Xiao, Yuqing
• Application Number:
  US14/480,556
• Publication Number:
  US 20150074380A1
• Time in Patent Office: 1,198 Days
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8053 Vector processors
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 2009/3883 Two-engine architectures, i.e. stand-alone processor acting as a slave processor
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3871 Asynchronous instruction pipeline, e.g. using handshake signals between stages
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3889 controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06F 9/3891 organised in groups of units sharing resources, e.g. clusters
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals

Abstract

A clock-less asynchronous processor comprising a plurality of parallel asynchronous processing logic circuits, each processing logic circuit configured to generate an instruction execution result. The processor comprises an asynchronous instruction dispatch unit coupled to each processing logic circuit, the instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the processing logic circuits. The processor comprises a crossbar coupled to an output of each processing logic circuit and to the dispatch unit, the crossbar configured to store the instruction execution results.

Claims

1. A clock-less asynchronous processor, comprising:

a plurality of parallel asynchronous processing unit cores, each parallel asynchronous processing unit core configured to generate an instruction execution result;

an asynchronous instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the parallel asynchronous processing unit cores;

a register file coupled to each asynchronous processing unit core, the register file configured to store the instruction execution results and provide each of the plurality of parallel asynchronous processing unit cores direct access to the instruction execution results stored at the register file; and

a crossbar coupled to each asynchronous processing unit core, the crossbar configured to store the instruction execution results and to bypass the register file, wherein bypassing the register file provides each of the plurality of parallel asynchronous processing unit cores direct access to the instruction execution results stored at the crossbar.

2. The clock-less asynchronous processor in accordance with claim 1, wherein the crossbar is further coupled to the asynchronous instruction dispatch unit.

3. The clock-less asynchronous processor in accordance with claim 2, wherein the register file is coupled to each asynchronous processing unit core and to the asynchronous instruction dispatch unit.

4. The clock-less asynchronous processor in accordance with claim 3, wherein:

in response to a first execution result currently stored in the crossbar, a given asynchronous processing unit core is configured to directly obtain the first execution result currently stored from the crossbar and bypass a fetch operation for the first execution result previously stored in the register file; and

in response to the first execution result not currently being stored in the crossbar, the given asynchronous processing unit core is configured to directly obtain the first execution result from the register file.

5. The clock-less asynchronous processor in accordance with claim 4, wherein the asynchronous instruction dispatch unit is coupled to each asynchronous processing unit core, and comprises:

a history table configured to indicate timing and data dependency information between the received multiple instructions; and

an instruction memory configured to distribute incoming instructions based on the timing and data dependency information between the received multiple instructions indicated by the history table.

6. The clock-less asynchronous processor in accordance with claim 1, wherein each asynchronous processing unit core is run-to-completed.

7. The clock-less asynchronous processor in accordance with claim 1, wherein each of the plurality of parallel asynchronous processing unit cores comprises a central processing unit (CPU) or an arithmetic logic unit (ALU).

8. The clock-less asynchronous processor in accordance with claim 2, further comprising a clock-less asynchronous coprocessor comprising a plurality of parallel second asynchronous processing unit cores, each second asynchronous processing unit core configured to generate a second instruction execution result.

9. The clock-less asynchronous processor in accordance with claim 8, wherein the clock-less asynchronous coprocessor is coupled to the crossbar, and wherein the asynchronous instruction dispatch unit is configured to detect data dependency for both the clock-less asynchronous processor and the clock-less asynchronous coprocessor.

10. The clock-less asynchronous processor in accordance with claim 9, wherein the crossbar is common to both the clock-less asynchronous processor and the clock-less asynchronous coprocessor, and wherein the crossbar is configured for use by both the clock-less asynchronous processor and the clock-less asynchronous coprocessor.

11. The clock-less asynchronous processor in accordance with claim 8, wherein the clock-less asynchronous processor comprises a first crossbar coupled to and dedicated for use by the clock-less asynchronous processor, and wherein the clock-less asynchronous coprocessor comprises a second crossbar coupled to and dedicated for use by the clock-less asynchronous coprocessor, the first crossbar separate and distinct from the second crossbar, and wherein the asynchronous instruction dispatch unit is configured to detect data dependency for both the clock-less asynchronous processor and the clock-less asynchronous coprocessor.

12. The clock-less asynchronous processor in accordance with claim 1, wherein each of the plurality of parallel asynchronous processing unit cores comprises multiple sequential processing stages.

13. A clock-less asynchronous processor, comprising:

a plurality of parallel asynchronous processing logic circuits, each parallel asynchronous processing logic circuit configured to generate an instruction execution result;

an asynchronous instruction dispatch unit coupled to each parallel asynchronous processing logic circuit, the asynchronous instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the parallel asynchronous processing logic circuits;

a register file coupled to each parallel asynchronous processing logic circuit, the register file configured to store the instruction execution results and provide each of the plurality of parallel asynchronous processing logic circuits direct access to the instruction execution results stored at the register file; and

a crossbar coupled to each parallel asynchronous processing logic circuit and to the asynchronous instruction dispatch unit, the crossbar configured to store the instruction execution results and to bypass the register file, wherein bypassing the register file provides each of the plurality of parallel asynchronous processing logic circuits direct access to the instruction execution results stored at the crossbar.

14. The clock-less asynchronous processor in accordance with claim 13, wherein each of the plurality of parallel asynchronous processing logic circuits comprises a central processing unit (CPU) or an arithmetic logic unit (ALU).

15. A method for operating an asynchronous processing system comprising a plurality of parallel asynchronous processing units, an asynchronous instruction dispatch unit coupled to each parallel asynchronous processing unit, a crossbar coupled to each parallel asynchronous processing unit and to the asynchronous instruction dispatch unit, and a register file coupled to each parallel asynchronous processing unit and to the asynchronous instruction dispatch unit, the method comprising:

receiving multiple instructions from memory and dispatching individual instructions to each of the parallel asynchronous processing units;

asynchronously processing a first instruction at a first parallel asynchronous processing unit of the parallel asynchronous processing units;

storing a first execution result from the first parallel asynchronous processing unit in the crossbar;

storing the first execution result from the first parallel asynchronous processing unit in the register file; and

in response to the first execution result being currently stored in the crossbar, directly obtaining the first execution result from the crossbar and bypassing a fetch operation for direct access to the first execution result stored in the register file.

16. The method in accordance with claim 15, further comprising

in response to the first execution result not currently being stored in the crossbar, obtaining the first execution result directly from the register file.

17. The method in accordance with claim 15, each of the plurality of parallel asynchronous processing units comprising a central processing unit (CPU) or an arithmetic logic unit (ALU), and the asynchronously processing the first instruction at the first parallel asynchronous processing unit comprising asynchronously processing the first instruction at a first CPU or ALU.

18. The method in accordance with claim 15, further comprising:

indicating a timing and data dependency information between the received multiple instructions; and

distributing incoming instructions based on the timing and data dependency information between the received multiple instructions.