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Systems and methods of memory bit flip identification for debugging and power management

  • US 9,846,612 B2
  • Filed: 08/11/2015
  • Issued: 12/19/2017
  • Est. Priority Date: 08/11/2015
  • Status: Expired due to Fees
First Claim
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1. A method for power management in a system on a chip (“

  • SoC”

    ), the method comprising;

    monitoring one or more parameters of the SoC that are associated with bit flips;

    calculating baseline parity values for data blocks of bits queued to be written to bit cell arrays of a random access memory (RAM) component and assigning the baseline parity values to parity bits uniquely associated with the data blocks;

    writing the data blocks to the bit cell arrays of the RAM component and a buffer of the RAM component;

    for each data block as it is written to the buffer, calculating a write-side parity value;

    for each data block, comparing its baseline parity value to its write-side parity value;

    for each data block, if the baseline parity value differs from the write-side parity value, recording the occurrence of a bit flip;

    based on determining that a rate of bit flip occurrences has exceeded a threshold, adjusting a thermal and power management policy associated with one or more thermally aggressive components of the SoC located in thermal proximity to the RAM component to reduce thermal energy generation by the one or more thermally aggressive components.

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