Detecting defects on a wafer using defect-specific and multi-channel information

• US 9,846,930 B2
• Filed: 12/12/2016
• Issued: 12/19/2017
• Est. Priority Date: 02/01/2013
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Wu, Kenong, Gao, Lisheng, Chen, Grace Hsiu-Ling, Shortt, David W.
• Primary Examiner(s): Alavi, Amir
• Application Number:
  US15/376,486
• Publication Number:
  US 20170091925A1
• Time in Patent Office: 372 Days
• CPC Class Codes: G01N 2021/8822 Dark field detection
• CPC Class Codes: G01N 2021/8848 Polarisation of light
• CPC Class Codes: G01N 21/8806 Specially adapted optical and illumination features
• CPC Class Codes: G01N 21/8851 Scan or image signal processing specially adapted therefor, e.g. for scan signal adjustment, for detecting different kinds of defects, for compensating for structures, markings, edges G01N21/8806 and G01N21/93 - G01N21/95692 take precedence; optical measurement of dimensions G01B11/00; optical scanning G02B26/10; image transformation G06T3/00; computerised image enhancement G06T5/00; image processing per se for flaw detection G06T7/0002
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0008 checking presence/absence
• CPC Class Codes: G06T 7/001 using an image reference approach
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Methods and systems for detecting defects on a wafer using defect-specific and multi-channel information are provided. One method includes acquiring information for a target on a wafer. The target includes a pattern of interest (POI) formed on the wafer and a known defect of interest (DOI) occurring proximate to or in the POI. The method also includes detecting the known DOI in target candidates by identifying potential DOI locations based on images of the target candidates acquired by a first channel of an inspection system and applying one or more detection parameters to images of the potential DOI locations acquired by a second channel of the inspection system. Therefore, the image(s) used for locating potential DOI locations and the image(s) used for detecting defects can be different.

Claims

1. A system configured to detect defects on a wafer, comprising:

an inspection subsystem configured to acquire information for a target on a wafer, wherein the inspection subsystem comprises at least first and second channels, wherein the target comprises a pattern of interest formed on the wafer and a known defect of interest occurring proximate to or in the pattern of interest, and wherein the information comprises a first image of the pattern of interest on the wafer acquired by imaging the pattern of interest on the wafer with the first channel of the inspection subsystem and a second image of the known defect of interest on the wafer acquired by imaging the known defect of interest with the second channel of the inspection subsystem;

wherein the inspection subsystem is further configured to search for target candidates on the wafer or on another wafer, wherein the target candidates comprise the pattern of interest; and

a computer system configured to detect the known defect of interest in the target candidates by identifying potential defect of interest locations based on images of the target candidates acquired by the first channel and applying one or more detection parameters to one or more images acquired by at least the second channel of the potential defect of interest locations.

2. The system of claim 1, wherein the known defect of interest is a defect that occurs repeatedly in certain patterns on the wafer.

3. The system of claim 1, wherein the known defect of interest is a systematic defect.

4. The system of claim 1, wherein the inspection subsystem is further configured as an electron beam inspection subsystem.

5. The system of claim 1, wherein the inspection subsystem is further configured as an electron beam inspection subsystem, and wherein the electron beam inspection subsystem collects images of the wafer in multiple modes.

6. The system of claim 1, wherein the inspection subsystem is further configured as an electron beam review subsystem.

7. The system of claim 1, wherein the inspection subsystem is further configured as an electron beam review subsystem, and wherein the electron beam review subsystem collects images of the wafer in multiple modes.

8. The system of claim 1, wherein the inspection subsystem comprises an imaging detector configured to detect light reflected from the wafer and to generate an image that is responsive to the reflected light detected by the detector.

9. The system of claim 1, wherein the inspection subsystem is further configured as a bright field inspection subsystem.

10. The system of claim 1, wherein the images of the target candidates acquired by the first channel comprise optical images, and wherein the computer system is further configured for identifying the potential defect of interest locations by correlating scanning electron microscope images of the known defect of interest to the optical images of the wafer.

11. The system of claim 1, wherein a location of the known defect of interest on the wafer is obtained based on optical images of the wafer.

12. The system of claim 1, wherein optical patch images are used as templates for the target.

13. The system of claim 1, wherein optical patch images are used to search for the target candidates.

14. The system of claim 1, wherein the computer system is further configured for determining one or more parameters of a care area for the wafer based on results of searching for the target candidates.

15. The system of claim 1, wherein the inspection subsystem is further configured to search for the target candidates using a bright field mode of the inspection subsystem.

16. The system of claim 1, wherein the computer system is further configured to define a micro care area based on locations of the target candidates identified by searching for the target candidates.

17. The system of claim 1, wherein the inspection subsystem is further configured for separate and simultaneous bright field and dark field collection.