Memory device and method for operating the same

• US 9,847,118 B1
• Filed: 12/21/2016
• Issued: 12/19/2017
• Est. Priority Date: 07/12/2016
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Won, Hyung-Sik
• Primary Examiner(s): Tran, Michael
• Application Number:
  US15/386,082
• Time in Patent Office: 363 Days
• Field of Search: 365222, 36523006
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406

Abstract

A memory device may include: a cell array comprising a main area and an adjacent area with a plurality of main memory cells disposed in the main area and a plurality of adjacent memory cells disposed in the adjacent area; a control circuit suitable for controlling a row operation and column operation of the cell array; and an adjacent area controller suitable for controlling adjacent memory cells so that the adjacent memory cells are operated under a different condition from the main memory cells.

Claims

1. A memory device comprising:

a cell array comprising a main area and an adjacent area with a plurality of main memory cells disposed in the main area and a plurality of adjacent memory cells disposed in the adjacent area;

a control circuit suitable for controlling a row operation and column operation of the cell array; and

an adjacent area controller suitable for controlling adjacent memory cells so that the adjacent memory cells are operated under a different condition from the main memory cells,

wherein the adjacent memory cells are disposed adjacent the control circuit and the adjacent area controller stores the addresses of the adjacent memory cells.

2. The memory device of claim 1, wherein the adjacent area controller controls the adjacent memory cells so that the adjacent memory cells are refreshed at a higher frequency than the main memory cells.

3. The memory device of claim 1, wherein the adjacent area controller controls the adjacent memory cells so that the adjacent memory cells start to be sensed at a later point of time than the main memory cells.

4. The memory device of claim 1, wherein the adjacent area controller controls the adjacent memory cells, so that a write operation for the adjacent memory cells is started at an earlier point of time or performed for a longer time than a write operation for the main memory cells.

5. The memory device of claim 1, wherein the cell array comprises:

a plurality of word lines; and

a plurality of bit lines.

6. The memory device of claim 5, wherein the adjacent area controller controls one or more word lines arranged in the area adjacent to the control circuit among the plurality of word lines, so that the one or more word lines are driven to a higher voltage than the main area word lines, during a refresh operation.

7. The memory device of claim 5, wherein the adjacent area controller controls one or more word lines arranged in the area adjacent to the control circuit among the plurality of word lines, so that the one or more word lines start to be driven at an earlier point of time than the main area word lines, during a refresh operation.

8. A memory device comprising:

a cell array comprising a plurality of sub cell arrays arranged in a matrix shape;

a control circuit suitable for controlling a row operation and column operation of the cell array; and

an adjacent area controller suitable for controlling all or part of memory cells included in sub cell arrays, which are arranged in an area adjacent to the control circuit, among the sub cell arrays, such that all or part of the memory cells are operated under a different condition from memory cells included in the other sub cell arrays,

wherein the adjacent area controller stores the addresses of the memory cells included in the sub cell arrays, which are arranged in the area adjacent to the control circuit.

9. The memory device of claim 8, wherein each of the sub cell arrays comprises:

a plurality of sub word lines; and

a plurality of bit lines.

10. The memory device of claim 9, wherein the control circuit comprises:

a row control unit suitable for controlling the row operation of the cell array; and

a column control unit suitable for controlling the column operation of the cell array.

11. The memory device of claim 10, wherein the adjacent area controller controls all or part of the plurality of sub word lines of one or more sub cell arrays adjacent to the control circuit among the sub cell arrays, so that all or part of the plurality of sub word lines are refreshed at a high frequency than the other sub word lines.

12. The memory device of claim 10, wherein the adjacent area controller controls all or part of the plurality of sub word lines of one or more sub cell arrays adjacent to the control circuit among the sub cell arrays, so that all or part of the plurality of sub word lines are driven to a higher voltage than the other sub word lines, during a refresh operation.

13. The memory device of claim 10, wherein the adjacent area controller controls all or part of the plurality of sub word lines of one or more sub cell arrays adjacent to the control circuit among the sub cell arrays, so that all or part of the plurality of sub word lines start to be driven at an earlier point of time than the other sub word lines, during a refresh operation.

14. The memory device of claim 10, wherein the adjacent area controller controls all or part of the plurality of bit lines of one or more sub cell arrays adjacent to the control circuit among the sub cell arrays, so that all or part of the plurality of bit lines start to be sensed at a later point of time than the other bit lines, during a read operation.

15. The memory device of claim 10, wherein the adjacent area controller controls all or part of the plurality of bit lines of one or more sub cell arrays adjacent to the control circuit among the sub cell arrays, so that all or part of the plurality of bit lines start to be driven at an earlier point of time or is driven for a longer time than the other bit lines, during a write operation.

16. A method for operating a memory device which includes a cell array including a plurality of memory cells, a control circuit for controlling a row operation and column operation of the cell array, and an adjacent area controller for controlling all or part of memory cells, the method comprising:

by the adjacent area controller, storing addresses of memory cells, which are arranged in an area adjacent to the control circuit, among the plurality of memory cells; and

by the adjacent are controller, controlling the memory cells, which are arranged in the area adjacent to the control circuit, so that the memory cells are operated under a different condition from the remaining memory cells of the memory cell array.

17. The method of claim 16, wherein the controlling of the memory cells comprises controlling the memory cells arranged in the area adjacent to the control circuit, so that the memory cells are refreshed at a higher frequency than the remaining memory cells the memory cell array.

18. The method of claim 16, wherein the controlling of the memory cells comprises controlling the memory cells arranged in the area adjacent to the control circuit, so that the memory cells start to be sensed at a later point of time than the remaining memory cells of the memory cell array, during a read operation.

19. The method of claim 16, wherein the controlling of the memory cells comprises controlling the memory cells arranged in the area adjacent to the control circuit, so that a write operation for the memory cells is started at an earlier point of time or performed for a longer time than a write operation for the remaining memory cells of the memory cell array, during a write operation.

20. A memory device comprising:

a cell array including a plurality of first and second memory cells;

a control circuit configured to control a row operation and column operation of the cell array; and

an adjacent area controller configured to control the plurality of second memory cells, so that the plurality of second memory cells are operated under a different condition from the plurality of first memory cells,

wherein the plurality of second memory cells are disposed between the control circuit and the plurality of first memory cells, and

wherein the adjacent area controller stores the addresses of the memory cells included in the second memory cells, which are arranged in the area adjacent to the control circuit.