Tunable negative bitline write assist and boost attenuation circuit
First Claim
1. A static random access memory (SRAM) write assist attenuation circuit, comprising:
- a clamping device comprising a first NFET, a second NFET, and a third NFET, wherein source-drain paths of the first NFET, the second NFET and the third NFET are connected in parallel to one another and are each connected to a common control signal; and
a logic structure comprising one or more OR gates configured to generate a first attenuation signal, a second attenuation signal, and a third attenuation signal,wherein the one or more OR gates are coupled to the first NFET, the second NFET, and the third NFET to provide the first attenuation signal, the second attenuation signal, and the third attenuation signal to the first NFET, the second NFET, and the third NFET, respectively, to attenuate an amount of boost applied to pull one of a plurality of true bit lines or one of a plurality of complement bit lines below ground in an active phase of a write cycle in response to at least one of the first attenuation signal, the second attenuation signal, and the third attenuation signal.
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Accused Products
Abstract
An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.
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Citations
14 Claims
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1. A static random access memory (SRAM) write assist attenuation circuit, comprising:
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a clamping device comprising a first NFET, a second NFET, and a third NFET, wherein source-drain paths of the first NFET, the second NFET and the third NFET are connected in parallel to one another and are each connected to a common control signal; and a logic structure comprising one or more OR gates configured to generate a first attenuation signal, a second attenuation signal, and a third attenuation signal, wherein the one or more OR gates are coupled to the first NFET, the second NFET, and the third NFET to provide the first attenuation signal, the second attenuation signal, and the third attenuation signal to the first NFET, the second NFET, and the third NFET, respectively, to attenuate an amount of boost applied to pull one of a plurality of true bit lines or one of a plurality of complement bit lines below ground in an active phase of a write cycle in response to at least one of the first attenuation signal, the second attenuation signal, and the third attenuation signal. - View Dependent Claims (2, 3, 4, 5, 6, 12, 13)
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7. A static random access memory (SRAM) device, comprising:
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a memory array comprising a plurality of SRAM cells; a plurality of true bit lines each connected to a column of the memory array; a plurality of complement bit lines each forming a differential pair with, and in a same column as, one of the plurality of true bit lines; a write driver connected to each of the differential pair of bit lines in each of the plurality of SRAM cells of the memory array; and a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising; a clamping device comprising a first NFET, a second NFET, and a third NFET connected to a common control signal; and a logic structure configured to generate a first attenuation signal, a second attenuation signal, and a third attenuation signal, wherein the logic structure is coupled to the first NFET, the second NFET, and the third NFET to provide the first attenuation signal, the second attenuation signal, and the third attenuation signal to the first NFET, the second NFET, and the third NFET, respectively, to attenuate an amount of boost applied to pull one of the plurality of true bit lines or one of the plurality of complement bit lines below ground in an active phase of a write cycle in response to at least one of the first attenuation signal, the second attenuation signal, and the third attenuation signal, wherein a width of a channel of each of the first NFET, the second NFET, and the third NFET is different such that each of the first NFET, the second NFET, and the third NFET modifies the common control signal in a different manner, and wherein the channel width of the first NFET is configured to provide a default attenuation to the amount of boost, the channel width of the second NFET is configured to provide an attenuation less than the default attenuation to the amount of boost, and the channel width of the third NFET is configured to provide an attenuation greater than the default attenuation to the amount of boost. - View Dependent Claims (8, 9, 10, 11, 14)
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Specification